| Message ID | 20210723234352.214459-1-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: fix not reading DSC disable fuse in GLK | expand |
On Fri, Jul 23, 2021 at 04:43:52PM -0700, Lucas De Marchi wrote: > We were using GRAPHICS_VER() to handle SKL_DFSM register, which means we > were not handling GLK correctly since that has GRAPHICS_VER == 9, but > DISPLAY_VER == 10. Switch the entire branch to check DISPLAY_VER > which makes it more in line with Bspec. > > Even though the Bspec has an exception for RKL in > TGL_DFSM_PIPE_D_DISABLE, we don't have to do anything as the bit has > disable semantic and RKL doesn't have pipe D. > > Bspec: 50075, 7548 > Fixes: 2b5a4562edd0 ("drm/i915/display: Simplify GLK display version tests") > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/intel_device_info.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index d5cf5977938a..99b51c292942 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -335,7 +335,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > info->pipe_mask &= ~BIT(PIPE_C); > info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); > } > - } else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) { > + } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { > u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); > > if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { > @@ -350,7 +350,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > info->pipe_mask &= ~BIT(PIPE_C); > info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); > } > - if (GRAPHICS_VER(dev_priv) >= 12 && > + > + if (DISPLAY_VER(dev_priv) >= 12 && > (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { > info->pipe_mask &= ~BIT(PIPE_D); > info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); > @@ -362,10 +363,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) > info->display.has_fbc = 0; > > - if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) > + if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) > info->display.has_dmc = 0; > > - if (GRAPHICS_VER(dev_priv) >= 10 && > + if (DISPLAY_VER(dev_priv) >= 10 && > (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) > info->display.has_dsc = 0; > } > -- > 2.31.1 >
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index d5cf5977938a..99b51c292942 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -335,7 +335,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) info->pipe_mask &= ~BIT(PIPE_C); info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); } - } else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) { + } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { @@ -350,7 +350,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) info->pipe_mask &= ~BIT(PIPE_C); info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); } - if (GRAPHICS_VER(dev_priv) >= 12 && + + if (DISPLAY_VER(dev_priv) >= 12 && (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { info->pipe_mask &= ~BIT(PIPE_D); info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); @@ -362,10 +363,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) info->display.has_fbc = 0; - if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) + if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) info->display.has_dmc = 0; - if (GRAPHICS_VER(dev_priv) >= 10 && + if (DISPLAY_VER(dev_priv) >= 10 && (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) info->display.has_dsc = 0; }
We were using GRAPHICS_VER() to handle SKL_DFSM register, which means we were not handling GLK correctly since that has GRAPHICS_VER == 9, but DISPLAY_VER == 10. Switch the entire branch to check DISPLAY_VER which makes it more in line with Bspec. Even though the Bspec has an exception for RKL in TGL_DFSM_PIPE_D_DISABLE, we don't have to do anything as the bit has disable semantic and RKL doesn't have pipe D. Bspec: 50075, 7548 Fixes: 2b5a4562edd0 ("drm/i915/display: Simplify GLK display version tests") Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/intel_device_info.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)