diff mbox series

[v2] hw/net: npcm7xx_emc fix missing queue_flush

Message ID 20211203221002.1719306-1-venture@google.com (mailing list archive)
State New, archived
Headers show
Series [v2] hw/net: npcm7xx_emc fix missing queue_flush | expand

Commit Message

Patrick Venture Dec. 3, 2021, 10:10 p.m. UTC
The rx_active boolean change to true should always trigger a try_read
call that flushes the queue.

Signed-off-by: Patrick Venture <venture@google.com>
---
v2: introduced helper method to encapsulate rx activation and queue flush.
---
 hw/net/npcm7xx_emc.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

Comments

Philippe Mathieu-Daudé Dec. 4, 2021, 9:45 a.m. UTC | #1
On 12/3/21 23:10, Patrick Venture wrote:
> The rx_active boolean change to true should always trigger a try_read
> call that flushes the queue.
> 
> Signed-off-by: Patrick Venture <venture@google.com>
> ---
> v2: introduced helper method to encapsulate rx activation and queue flush.

Thanks,

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  hw/net/npcm7xx_emc.c | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
Peter Maydell Dec. 10, 2021, 4:47 p.m. UTC | #2
On Fri, 3 Dec 2021 at 22:10, Patrick Venture <venture@google.com> wrote:
>
> The rx_active boolean change to true should always trigger a try_read
> call that flushes the queue.
>
> Signed-off-by: Patrick Venture <venture@google.com>
> ---
> v2: introduced helper method to encapsulate rx activation and queue flush.
> ---
>  hw/net/npcm7xx_emc.c | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
>

Applied to target-arm.next for 7.0, thanks.

-- PMM
diff mbox series

Patch

diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
index 7c892f820f..545b2b7410 100644
--- a/hw/net/npcm7xx_emc.c
+++ b/hw/net/npcm7xx_emc.c
@@ -284,6 +284,12 @@  static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag)
     emc_set_mista(emc, mista_flag);
 }
 
+static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc)
+{
+    emc->rx_active = true;
+    qemu_flush_queued_packets(qemu_get_queue(emc->nic));
+}
+
 static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc,
                                        const NPCM7xxEMCTxDesc *tx_desc,
                                        uint32_t desc_addr)
@@ -581,13 +587,6 @@  static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1)
     return len;
 }
 
-static void emc_try_receive_next_packet(NPCM7xxEMCState *emc)
-{
-    if (emc_can_receive(qemu_get_queue(emc->nic))) {
-        qemu_flush_queued_packets(qemu_get_queue(emc->nic));
-    }
-}
-
 static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size)
 {
     NPCM7xxEMCState *emc = opaque;
@@ -703,7 +702,7 @@  static void npcm7xx_emc_write(void *opaque, hwaddr offset,
             emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA;
         }
         if (value & REG_MCMDR_RXON) {
-            emc->rx_active = true;
+            emc_enable_rx_and_flush(emc);
         } else {
             emc_halt_rx(emc, 0);
         }
@@ -739,8 +738,7 @@  static void npcm7xx_emc_write(void *opaque, hwaddr offset,
         break;
     case REG_RSDR:
         if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) {
-            emc->rx_active = true;
-            emc_try_receive_next_packet(emc);
+            emc_enable_rx_and_flush(emc);
         }
         break;
     case REG_MIIDA: