| Message ID | 20211230123539.52786-6-anup@brainfault.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
Anup Patel <anup@brainfault.org> 於 2021年12月30日 週四 下午8:36寫道： > From: Anup Patel <anup.patel@wdc.com> > > The machine or device emulation should be able to force set certain > CPU features because: > 1) We can have certain CPU features which are in-general optional > but implemented by RISC-V CPUs on the machine. > 2) We can have devices which require a certain CPU feature. For example, > AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Signed-off-by: Anup Patel <anup@brainfault.org> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 11 +++-------- > target/riscv/cpu.h | 5 +++++ > 2 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f4dbc766c2..9f1a4d1088 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -124,11 +124,6 @@ static void set_vext_version(CPURISCVState *env, int > vext_ver) > env->vext_ver = vext_ver; > } > > -static void set_feature(CPURISCVState *env, int feature) > -{ > - env->features |= (1ULL << feature); > -} > - > static void set_resetvec(CPURISCVState *env, target_ulong resetvec) > { > #ifndef CONFIG_USER_ONLY > @@ -434,18 +429,18 @@ static void riscv_cpu_realize(DeviceState *dev, > Error **errp) > } > > if (cpu->cfg.mmu) { > - set_feature(env, RISCV_FEATURE_MMU); > + riscv_set_feature(env, RISCV_FEATURE_MMU); > } > > if (cpu->cfg.pmp) { > - set_feature(env, RISCV_FEATURE_PMP); > + riscv_set_feature(env, RISCV_FEATURE_PMP); > > /* > * Enhanced PMP should only be available > * on harts with PMP support > */ > if (cpu->cfg.epmp) { > - set_feature(env, RISCV_FEATURE_EPMP); > + riscv_set_feature(env, RISCV_FEATURE_EPMP); > } > } > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6895ac138c..1bdd03731f 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -344,6 +344,11 @@ static inline bool riscv_feature(CPURISCVState *env, > int feature) > return env->features & (1ULL << feature); > } > > +static inline void riscv_set_feature(CPURISCVState *env, int feature) > +{ > + env->features |= (1ULL << feature); > +} > + > #include "cpu_user.h" > > extern const char * const riscv_int_regnames[]; > -- > 2.25.1 > > > Reviewed-by: Frank Chang <frank.chang@sifive.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f4dbc766c2..9f1a4d1088 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -124,11 +124,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } -static void set_feature(CPURISCVState *env, int feature) -{ - env->features |= (1ULL << feature); -} - static void set_resetvec(CPURISCVState *env, target_ulong resetvec) { #ifndef CONFIG_USER_ONLY @@ -434,18 +429,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.mmu) { - set_feature(env, RISCV_FEATURE_MMU); + riscv_set_feature(env, RISCV_FEATURE_MMU); } if (cpu->cfg.pmp) { - set_feature(env, RISCV_FEATURE_PMP); + riscv_set_feature(env, RISCV_FEATURE_PMP); /* * Enhanced PMP should only be available * on harts with PMP support */ if (cpu->cfg.epmp) { - set_feature(env, RISCV_FEATURE_EPMP); + riscv_set_feature(env, RISCV_FEATURE_EPMP); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6895ac138c..1bdd03731f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -344,6 +344,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) return env->features & (1ULL << feature); } +static inline void riscv_set_feature(CPURISCVState *env, int feature) +{ + env->features |= (1ULL << feature); +} + #include "cpu_user.h" extern const char * const riscv_int_regnames[];