| Message ID | 20220411072340.740981-1-conor.dooley@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] clk: microchip: mpfs: don't reset disabled peripherals | expand |
Quoting Conor Dooley (2022-04-11 00:23:41) > The current clock driver for PolarFire SoC puts the hardware behind > "periph" clocks into reset if their clock is disabled. CONFIG_PM was > recently added to the riscv defconfig and exposed issues caused by this > behaviour, where the Cadence GEM was being put into reset between its > bringup & the PHY bringup: > > https://lore.kernel.org/linux-riscv/9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com/ > > Fix this (for now) by removing the reset from mpfs_periph_clk_disable. > > Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") > Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- Applied to clk-fixes
On 22/04/2022 02:35, Stephen Boyd wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Quoting Conor Dooley (2022-04-11 00:23:41) >> The current clock driver for PolarFire SoC puts the hardware behind >> "periph" clocks into reset if their clock is disabled. CONFIG_PM was >> recently added to the riscv defconfig and exposed issues caused by this >> behaviour, where the Cadence GEM was being put into reset between its >> bringup & the PHY bringup: >> >> https://lore.kernel.org/linux-riscv/9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com/ >> >> Fix this (for now) by removing the reset from mpfs_periph_clk_disable. >> >> Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") >> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- > > Applied to clk-fixes thanks!
diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index aa1561b773d6..744ef2ba2a0c 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -200,10 +200,6 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw) spin_lock_irqsave(&mpfs_clk_lock, flags); - reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - val = reg | (1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); val = reg & ~(1u << periph->shift); writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
The current clock driver for PolarFire SoC puts the hardware behind "periph" clocks into reset if their clock is disabled. CONFIG_PM was recently added to the riscv defconfig and exposed issues caused by this behaviour, where the Cadence GEM was being put into reset between its bringup & the PHY bringup: https://lore.kernel.org/linux-riscv/9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com/ Fix this (for now) by removing the reset from mpfs_periph_clk_disable. Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Changes since v1: The first stage bootloader takes most, but not all, of the peripherals out of reset. In v1 all code touching the reset reg was removed, but in v2 the code taking peripherals out of reset is kept to cover the edge case peripherals. The permanent fix will be to move the reset stuff its own driver. drivers/clk/microchip/clk-mpfs.c | 4 ---- 1 file changed, 4 deletions(-)