diff mbox series

[v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order

Message ID 20220516102217.25960-1-bharat.kumar.gogada@xilinx.com (mailing list archive)
State Accepted
Commit e2c6170a55baefcbeb477e06e66f07659ea4f58d
Headers show
Series [v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order | expand

Commit Message

Bharat Kumar Gogada May 16, 2022, 10:22 a.m. UTC
All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.

This order is also suggested by node name which is pcie@fca10000 which
suggests that cpm_slcr register should be the first.

Driver itself is using devm_platform_ioremap_resource_byname() for both
names that's why there is no functional change even on description which
are using current order.

But still prefer to change order to cover currently used description.
Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port")

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
 .../devicetree/bindings/pci/xilinx-versal-cpm.yaml     | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Michal Simek May 16, 2022, 11:17 a.m. UTC | #1
On 5/16/22 12:22, Bharat Kumar Gogada wrote:
> All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.
> 
> This order is also suggested by node name which is pcie@fca10000 which
> suggests that cpm_slcr register should be the first.
> 
> Driver itself is using devm_platform_ioremap_resource_byname() for both
> names that's why there is no functional change even on description which
> are using current order.
> 
> But still prefer to change order to cover currently used description.
> Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port")
> 
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
>   .../devicetree/bindings/pci/xilinx-versal-cpm.yaml     | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> index 32f4641085bc..cca395317a4c 100644
> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> @@ -18,13 +18,13 @@ properties:
>   
>     reg:
>       items:
> -      - description: Configuration space region and bridge registers.
>         - description: CPM system level control and status registers.
> +      - description: Configuration space region and bridge registers.
>   
>     reg-names:
>       items:
> -      - const: cfg
>         - const: cpm_slcr
> +      - const: cfg
>   
>     interrupts:
>       maxItems: 1
> @@ -86,9 +86,9 @@ examples:
>                          ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
>                                   <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
>                          msi-map = <0x0 &its_gic 0x0 0x10000>;
> -                       reg = <0x6 0x00000000 0x0 0x10000000>,
> -                             <0x0 0xfca10000 0x0 0x1000>;
> -                       reg-names = "cfg", "cpm_slcr";
> +                       reg = <0x0 0xfca10000 0x0 0x1000>,
> +                             <0x6 0x00000000 0x0 0x10000000>;
> +                       reg-names = "cpm_slcr", "cfg";
>                          pcie_intc_0: interrupt-controller {
>                                  #address-cells = <0>;
>                                  #interrupt-cells = <1>;

Reviewed-by: Michal Simek <michal.simek@amd.com>

Thanks,
Michal
Bharat Kumar Gogada May 25, 2022, 11:03 a.m. UTC | #2
Hi Rob,

Can you please check this.

Regards,
Bharat

> 
> On 5/16/22 12:22, Bharat Kumar Gogada wrote:
> > All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.
> >
> > This order is also suggested by node name which is pcie@fca10000 which
> > suggests that cpm_slcr register should be the first.
> >
> > Driver itself is using devm_platform_ioremap_resource_byname() for
> > both names that's why there is no functional change even on
> > description which are using current order.
> >
> > But still prefer to change order to cover currently used description.
> > Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM
> > Root Port")
> >
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > ---
> >   .../devicetree/bindings/pci/xilinx-versal-cpm.yaml     | 10 +++++-----
> >   1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > index 32f4641085bc..cca395317a4c 100644
> > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > @@ -18,13 +18,13 @@ properties:
> >
> >     reg:
> >       items:
> > -      - description: Configuration space region and bridge registers.
> >         - description: CPM system level control and status registers.
> > +      - description: Configuration space region and bridge registers.
> >
> >     reg-names:
> >       items:
> > -      - const: cfg
> >         - const: cpm_slcr
> > +      - const: cfg
> >
> >     interrupts:
> >       maxItems: 1
> > @@ -86,9 +86,9 @@ examples:
> >                          ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0
> 0x10000000>,
> >                                   <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0
> 0x80000000>;
> >                          msi-map = <0x0 &its_gic 0x0 0x10000>;
> > -                       reg = <0x6 0x00000000 0x0 0x10000000>,
> > -                             <0x0 0xfca10000 0x0 0x1000>;
> > -                       reg-names = "cfg", "cpm_slcr";
> > +                       reg = <0x0 0xfca10000 0x0 0x1000>,
> > +                             <0x6 0x00000000 0x0 0x10000000>;
> > +                       reg-names = "cpm_slcr", "cfg";
> >                          pcie_intc_0: interrupt-controller {
> >                                  #address-cells = <0>;
> >                                  #interrupt-cells = <1>;
> 
> Reviewed-by: Michal Simek <michal.simek@amd.com>
> 
> Thanks,
> Michal
Rob Herring (Arm) June 1, 2022, 7:53 p.m. UTC | #3
On Wed, May 25, 2022 at 11:03:32AM +0000, Bharat Kumar Gogada wrote:
> Hi Rob,
> 
> Can you please check this.

You can look at patchwork[1] and see where your patch is in the queue. 
No need to send me more emails.

Rob

[1] https://patchwork.ozlabs.org/project/devicetree-bindings/list/

> 
> Regards,
> Bharat
> 
> > 
> > On 5/16/22 12:22, Bharat Kumar Gogada wrote:
> > > All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.
> > >
> > > This order is also suggested by node name which is pcie@fca10000 which
> > > suggests that cpm_slcr register should be the first.
> > >
> > > Driver itself is using devm_platform_ioremap_resource_byname() for
> > > both names that's why there is no functional change even on
> > > description which are using current order.
> > >
> > > But still prefer to change order to cover currently used description.
> > > Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM
> > > Root Port")
> > >
> > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > > ---
> > >   .../devicetree/bindings/pci/xilinx-versal-cpm.yaml     | 10 +++++-----
> > >   1 file changed, 5 insertions(+), 5 deletions(-)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > > index 32f4641085bc..cca395317a4c 100644
> > > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > > @@ -18,13 +18,13 @@ properties:
> > >
> > >     reg:
> > >       items:
> > > -      - description: Configuration space region and bridge registers.
> > >         - description: CPM system level control and status registers.
> > > +      - description: Configuration space region and bridge registers.
> > >
> > >     reg-names:
> > >       items:
> > > -      - const: cfg
> > >         - const: cpm_slcr
> > > +      - const: cfg
> > >
> > >     interrupts:
> > >       maxItems: 1
> > > @@ -86,9 +86,9 @@ examples:
> > >                          ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0
> > 0x10000000>,
> > >                                   <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0
> > 0x80000000>;
> > >                          msi-map = <0x0 &its_gic 0x0 0x10000>;
> > > -                       reg = <0x6 0x00000000 0x0 0x10000000>,
> > > -                             <0x0 0xfca10000 0x0 0x1000>;
> > > -                       reg-names = "cfg", "cpm_slcr";
> > > +                       reg = <0x0 0xfca10000 0x0 0x1000>,
> > > +                             <0x6 0x00000000 0x0 0x10000000>;
> > > +                       reg-names = "cpm_slcr", "cfg";
> > >                          pcie_intc_0: interrupt-controller {
> > >                                  #address-cells = <0>;
> > >                                  #interrupt-cells = <1>;
> > 
> > Reviewed-by: Michal Simek <michal.simek@amd.com>
> > 
> > Thanks,
> > Michal
Rob Herring (Arm) June 1, 2022, 7:55 p.m. UTC | #4
On Mon, 16 May 2022 15:52:17 +0530, Bharat Kumar Gogada wrote:
> All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.
> 
> This order is also suggested by node name which is pcie@fca10000 which
> suggests that cpm_slcr register should be the first.
> 
> Driver itself is using devm_platform_ioremap_resource_byname() for both
> names that's why there is no functional change even on description which
> are using current order.
> 
> But still prefer to change order to cover currently used description.
> Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port")
> 
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
>  .../devicetree/bindings/pci/xilinx-versal-cpm.yaml     | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 

Applied, thanks!
Bharat Kumar Gogada June 3, 2022, 4:52 a.m. UTC | #5
> Subject: Re: [PATCH v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order
> 
> On Mon, 16 May 2022 15:52:17 +0530, Bharat Kumar Gogada wrote:
> > All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.
> >
> > This order is also suggested by node name which is pcie@fca10000 which
> > suggests that cpm_slcr register should be the first.
> >
> > Driver itself is using devm_platform_ioremap_resource_byname() for
> > both names that's why there is no functional change even on
> > description which are using current order.
> >
> > But still prefer to change order to cover currently used description.
> > Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM
> > Root Port")
> >
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > ---
> >  .../devicetree/bindings/pci/xilinx-versal-cpm.yaml     | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> 
> Applied, thanks!

Thanks Rob.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index 32f4641085bc..cca395317a4c 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -18,13 +18,13 @@  properties:
 
   reg:
     items:
-      - description: Configuration space region and bridge registers.
       - description: CPM system level control and status registers.
+      - description: Configuration space region and bridge registers.
 
   reg-names:
     items:
-      - const: cfg
       - const: cpm_slcr
+      - const: cfg
 
   interrupts:
     maxItems: 1
@@ -86,9 +86,9 @@  examples:
                        ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
                                 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
                        msi-map = <0x0 &its_gic 0x0 0x10000>;
-                       reg = <0x6 0x00000000 0x0 0x10000000>,
-                             <0x0 0xfca10000 0x0 0x1000>;
-                       reg-names = "cfg", "cpm_slcr";
+                       reg = <0x0 0xfca10000 0x0 0x1000>,
+                             <0x6 0x00000000 0x0 0x10000000>;
+                       reg-names = "cpm_slcr", "cfg";
                        pcie_intc_0: interrupt-controller {
                                #address-cells = <0>;
                                #interrupt-cells = <1>;