| Message ID | 20220815050815.22340-7-samuel@sholland.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Allwinner D1 platform support | expand |
On Mon, 15 Aug 2022 00:08:09 -0500 Samuel Holland <samuel@sholland.org> wrote: Hi, thanks for all the efforts in getting those SoC peripherals supported! > D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as > one HiFi 4 DSP. The SoC is based on a design that additionally contained > a pair of Cortex A7's. For that reason, some peripherals are duplicated. So because of this, the Allwinner R528 and T113 SoCs would share almost everything in this file. Would it be useful to already split this DT up? To have a base .dtsi, basically this file without /cpus and /soc/plic, then have a RISC-V specific file with just those, including the base? There is precedence for this across-arch(-directories) sharing with the Raspberry Pi and Allwinner H3/H5 SoCs. Or do you plan to leave that for when support for the ARM core versions is actually submitted? But I don't think we need any extra *code* for that, it's just the DT? Cheers, Andre. > > This devicetree includes all of the peripherals that already have a > documented binding. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/allwinner/Makefile | 1 + > arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++ > 3 files changed, 902 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/Makefile > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..f292e31bdb2c 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += allwinner > subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile > new file mode 100644 > index 000000000000..f66554cd5c45 > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/Makefile > @@ -0,0 +1 @@ > +# SPDX-License-Identifier: GPL-2.0 > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > new file mode 100644 > index 000000000000..d1429274f22e > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > @@ -0,0 +1,900 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> > + > +#include <dt-bindings/clock/sun6i-rtc.h> > +#include <dt-bindings/clock/sun8i-de2.h> > +#include <dt-bindings/clock/sun8i-tcon-top.h> > +#include <dt-bindings/clock/sun20i-d1-ccu.h> > +#include <dt-bindings/clock/sun20i-d1-r-ccu.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/reset/sun8i-de2.h> > +#include <dt-bindings/reset/sun20i-d1-ccu.h> > +#include <dt-bindings/reset/sun20i-d1-r-ccu.h> > +#include <dt-bindings/thermal/thermal.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <24000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + clocks = <&ccu CLK_RISCV>; > + clock-frequency = <24000000>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + #cooling-cells = <2>; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + de: display-engine { > + compatible = "allwinner,sun20i-d1-display-engine"; > + allwinner,pipelines = <&mixer0>, <&mixer1>; > + status = "disabled"; > + }; > + > + osc24M: osc24M-clk { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + dsp_wdt: watchdog@1700400 { > + compatible = "allwinner,sun20i-d1-wdt"; > + reg = <0x1700400 0x20>; > + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>, <&rtc CLK_OSC32K>; > + clock-names = "hosc", "losc"; > + status = "reserved"; > + }; > + > + pio: pinctrl@2000000 { > + compatible = "allwinner,sun20i-d1-pinctrl"; > + reg = <0x2000000 0x800>; > + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>, > + <87 IRQ_TYPE_LEVEL_HIGH>, > + <89 IRQ_TYPE_LEVEL_HIGH>, > + <91 IRQ_TYPE_LEVEL_HIGH>, > + <93 IRQ_TYPE_LEVEL_HIGH>, > + <95 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_APB0>, > + <&osc24M>, > + <&rtc CLK_OSC32K>; > + clock-names = "apb", "hosc", "losc"; > + gpio-controller; > + interrupt-controller; > + #gpio-cells = <3>; > + #interrupt-cells = <3>; > + > + /omit-if-no-ref/ > + i2c0_pb10_pins: i2c0-pb10-pins { > + pins = "PB10", "PB11"; > + function = "i2c0"; > + }; > + > + /omit-if-no-ref/ > + i2c2_pb0_pins: i2c2-pb0-pins { > + pins = "PB0", "PB1"; > + function = "i2c2"; > + }; > + > + /omit-if-no-ref/ > + lcd_rgb666_pins: lcd-rgb666-pins { > + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", > + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", > + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", > + "PD18", "PD19", "PD20", "PD21"; > + function = "lcd0"; > + }; > + > + /omit-if-no-ref/ > + mmc0_pins: mmc0-pins { > + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; > + function = "mmc0"; > + }; > + > + /omit-if-no-ref/ > + mmc1_pins: mmc1-pins { > + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; > + function = "mmc1"; > + }; > + > + /omit-if-no-ref/ > + mmc2_pins: mmc2-pins { > + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; > + function = "mmc2"; > + }; > + > + /omit-if-no-ref/ > + rgmii_pe_pins: rgmii-pe-pins { > + pins = "PE0", "PE1", "PE2", "PE3", "PE4", > + "PE5", "PE6", "PE7", "PE8", "PE9", > + "PE11", "PE12", "PE13", "PE14", "PE15"; > + function = "emac"; > + }; > + > + /omit-if-no-ref/ > + rmii_pe_pins: rmii-pe-pins { > + pins = "PE0", "PE1", "PE2", "PE3", "PE4", > + "PE5", "PE6", "PE7", "PE8", "PE9"; > + function = "emac"; > + }; > + > + /omit-if-no-ref/ > + uart0_pb8_pins: uart0-pb8-pins { > + pins = "PB8", "PB9"; > + function = "uart0"; > + }; > + > + /omit-if-no-ref/ > + uart1_pg6_pins: uart1-pg6-pins { > + pins = "PG6", "PG7"; > + function = "uart1"; > + }; > + > + /omit-if-no-ref/ > + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { > + pins = "PG8", "PG9"; > + function = "uart1"; > + }; > + }; > + > + ccu: clock-controller@2001000 { > + compatible = "allwinner,sun20i-d1-ccu"; > + reg = <0x2001000 0x1000>; > + clocks = <&osc24M>, > + <&rtc CLK_OSC32K>, > + <&rtc CLK_IOSC>; > + clock-names = "hosc", "losc", "iosc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + lradc: keys@2009800 { > + compatible = "allwinner,sun20i-d1-lradc", > + "allwinner,sun50i-r329-lradc"; > + reg = <0x2009800 0x400>; > + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_LRADC>; > + resets = <&ccu RST_BUS_LRADC>; > + status = "disabled"; > + }; > + > + codec: audio-codec@2030000 { > + compatible = "simple-mfd", "syscon"; > + reg = <0x2030000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + regulators@2030348 { > + compatible = "allwinner,sun20i-d1-analog-ldos"; > + reg = <0x2030348 0x4>; > + nvmem-cells = <&bg_trim>; > + nvmem-cell-names = "bg_trim"; > + > + reg_aldo: aldo { > + }; > + > + reg_hpldo: hpldo { > + }; > + }; > + }; > + > + i2s0: i2s@2032000 { > + compatible = "allwinner,sun20i-d1-i2s", > + "allwinner,sun50i-r329-i2s"; > + reg = <0x2032000 0x1000>; > + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2S0>, > + <&ccu CLK_I2S0>; > + clock-names = "apb", "mod"; > + resets = <&ccu RST_BUS_I2S0>; > + dmas = <&dma 3>, <&dma 3>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #sound-dai-cells = <0>; > + }; > + > + i2s1: i2s@2033000 { > + compatible = "allwinner,sun20i-d1-i2s", > + "allwinner,sun50i-r329-i2s"; > + reg = <0x2033000 0x1000>; > + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2S1>, > + <&ccu CLK_I2S1>; > + clock-names = "apb", "mod"; > + resets = <&ccu RST_BUS_I2S1>; > + dmas = <&dma 4>, <&dma 4>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #sound-dai-cells = <0>; > + }; > + > + i2s2: i2s@2034000 { > + compatible = "allwinner,sun20i-d1-i2s", > + "allwinner,sun50i-r329-i2s"; > + reg = <0x2034000 0x1000>; > + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2S2>, > + <&ccu CLK_I2S2>; > + clock-names = "apb", "mod"; > + resets = <&ccu RST_BUS_I2S2>; > + dmas = <&dma 5>, <&dma 5>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #sound-dai-cells = <0>; > + }; > + > + timer: timer@2050000 { > + compatible = "allwinner,sun20i-d1-timer", > + "allwinner,sun8i-a23-timer"; > + reg = <0x2050000 0xa0>; > + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>, > + <76 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>; > + }; > + > + wdt: watchdog@20500a0 { > + compatible = "allwinner,sun20i-d1-wdt-reset", > + "allwinner,sun20i-d1-wdt"; > + reg = <0x20500a0 0x20>; > + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>, <&rtc CLK_OSC32K>; > + clock-names = "hosc", "losc"; > + status = "reserved"; > + }; > + > + uart0: serial@2500000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2500000 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART0>; > + resets = <&ccu RST_BUS_UART0>; > + dmas = <&dma 14>, <&dma 14>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart1: serial@2500400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2500400 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART1>; > + resets = <&ccu RST_BUS_UART1>; > + dmas = <&dma 15>, <&dma 15>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart2: serial@2500800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2500800 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART2>; > + resets = <&ccu RST_BUS_UART2>; > + dmas = <&dma 16>, <&dma 16>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart3: serial@2500c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2500c00 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART3>; > + resets = <&ccu RST_BUS_UART3>; > + dmas = <&dma 17>, <&dma 17>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart4: serial@2501000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2501000 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART4>; > + resets = <&ccu RST_BUS_UART4>; > + dmas = <&dma 18>, <&dma 18>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart5: serial@2501400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2501400 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART5>; > + resets = <&ccu RST_BUS_UART5>; > + dmas = <&dma 19>, <&dma 19>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + i2c0: i2c@2502000 { > + compatible = "allwinner,sun20i-d1-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x2502000 0x400>; > + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + dmas = <&dma 43>, <&dma 43>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c1: i2c@2502400 { > + compatible = "allwinner,sun20i-d1-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x2502400 0x400>; > + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + dmas = <&dma 44>, <&dma 44>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c2: i2c@2502800 { > + compatible = "allwinner,sun20i-d1-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x2502800 0x400>; > + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + dmas = <&dma 45>, <&dma 45>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c3: i2c@2502c00 { > + compatible = "allwinner,sun20i-d1-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x2502c00 0x400>; > + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C3>; > + resets = <&ccu RST_BUS_I2C3>; > + dmas = <&dma 46>, <&dma 46>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + syscon: syscon@3000000 { > + compatible = "allwinner,sun20i-d1-system-control"; > + reg = <0x3000000 0x1000>; > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + > + regulators@3000150 { > + compatible = "allwinner,sun20i-d1-system-ldos"; > + reg = <0x3000150 0x4>; > + > + reg_ldoa: ldoa { > + }; > + > + reg_ldob: ldob { > + }; > + }; > + }; > + > + dma: dma-controller@3002000 { > + compatible = "allwinner,sun20i-d1-dma"; > + reg = <0x3002000 0x1000>; > + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; > + clock-names = "bus", "mbus"; > + resets = <&ccu RST_BUS_DMA>; > + dma-channels = <16>; > + dma-requests = <48>; > + #dma-cells = <1>; > + }; > + > + sid: efuse@3006000 { > + compatible = "allwinner,sun20i-d1-sid"; > + reg = <0x3006000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + ths_calib: ths-calib@14 { > + reg = <0x14 0x4>; > + }; > + > + bg_trim: bg-trim@28 { > + reg = <0x28 0x4>; > + bits = <16 8>; > + }; > + }; > + > + mbus: dram-controller@3102000 { > + compatible = "allwinner,sun20i-d1-mbus"; > + reg = <0x3102000 0x1000>, > + <0x3103000 0x1000>; > + reg-names = "mbus", "dram"; > + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_MBUS>, > + <&ccu CLK_DRAM>, > + <&ccu CLK_BUS_DRAM>; > + clock-names = "mbus", "dram", "bus"; > + dma-ranges = <0 0x40000000 0x80000000>; > + #address-cells = <1>; > + #size-cells = <1>; > + #interconnect-cells = <1>; > + }; > + > + mmc0: mmc@4020000 { > + compatible = "allwinner,sun20i-d1-mmc"; > + reg = <0x4020000 0x1000>; > + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC0>; > + reset-names = "ahb"; > + cap-sd-highspeed; > + max-frequency = <150000000>; > + no-mmc; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc1: mmc@4021000 { > + compatible = "allwinner,sun20i-d1-mmc"; > + reg = <0x4021000 0x1000>; > + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC1>; > + reset-names = "ahb"; > + cap-sd-highspeed; > + max-frequency = <150000000>; > + no-mmc; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc2: mmc@4022000 { > + compatible = "allwinner,sun20i-d1-emmc", > + "allwinner,sun50i-a100-emmc"; > + reg = <0x4022000 0x1000>; > + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC2>; > + reset-names = "ahb"; > + cap-mmc-highspeed; > + max-frequency = <150000000>; > + mmc-ddr-1_8v; > + mmc-ddr-3_3v; > + no-sd; > + no-sdio; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + usb_otg: usb@4100000 { > + compatible = "allwinner,sun20i-d1-musb", > + "allwinner,sun8i-a33-musb"; > + reg = <0x4100000 0x400>; > + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mc"; > + clocks = <&ccu CLK_BUS_OTG>; > + resets = <&ccu RST_BUS_OTG>; > + extcon = <&usbphy 0>; > + phys = <&usbphy 0>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + usbphy: phy@4100400 { > + compatible = "allwinner,sun20i-d1-usb-phy"; > + reg = <0x4100400 0x100>, > + <0x4101800 0x100>, > + <0x4200800 0x100>; > + reg-names = "phy_ctrl", > + "pmu0", > + "pmu1"; > + clocks = <&osc24M>, > + <&osc24M>; > + clock-names = "usb0_phy", > + "usb1_phy"; > + resets = <&ccu RST_USB_PHY0>, > + <&ccu RST_USB_PHY1>; > + reset-names = "usb0_reset", > + "usb1_reset"; > + status = "disabled"; > + #phy-cells = <1>; > + }; > + > + ehci0: usb@4101000 { > + compatible = "allwinner,sun20i-d1-ehci", > + "generic-ehci"; > + reg = <0x4101000 0x100>; > + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_BUS_EHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets = <&ccu RST_BUS_OHCI0>, > + <&ccu RST_BUS_EHCI0>; > + phys = <&usbphy 0>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci0: usb@4101400 { > + compatible = "allwinner,sun20i-d1-ohci", > + "generic-ohci"; > + reg = <0x4101400 0x100>; > + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets = <&ccu RST_BUS_OHCI0>; > + phys = <&usbphy 0>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ehci1: usb@4200000 { > + compatible = "allwinner,sun20i-d1-ehci", > + "generic-ehci"; > + reg = <0x4200000 0x100>; > + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_BUS_EHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets = <&ccu RST_BUS_OHCI1>, > + <&ccu RST_BUS_EHCI1>; > + phys = <&usbphy 1>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci1: usb@4200400 { > + compatible = "allwinner,sun20i-d1-ohci", > + "generic-ohci"; > + reg = <0x4200400 0x100>; > + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets = <&ccu RST_BUS_OHCI1>; > + phys = <&usbphy 1>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + emac: ethernet@4500000 { > + compatible = "allwinner,sun20i-d1-emac", > + "allwinner,sun50i-a64-emac"; > + reg = <0x4500000 0x10000>; > + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq"; > + clocks = <&ccu CLK_BUS_EMAC>; > + clock-names = "stmmaceth"; > + resets = <&ccu RST_BUS_EMAC>; > + reset-names = "stmmaceth"; > + syscon = <&syscon>; > + status = "disabled"; > + > + mdio: mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + display_clocks: clock-controller@5000000 { > + compatible = "allwinner,sun20i-d1-de2-clk", > + "allwinner,sun50i-h5-de2-clk"; > + reg = <0x5000000 0x10000>; > + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_DE>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + mixer0: mixer@5100000 { > + compatible = "allwinner,sun20i-d1-de2-mixer-0"; > + reg = <0x5100000 0x100000>; > + clocks = <&display_clocks CLK_BUS_MIXER0>, > + <&display_clocks CLK_MIXER0>; > + clock-names = "bus", "mod"; > + resets = <&display_clocks RST_MIXER0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mixer0_out: port@1 { > + reg = <1>; > + > + mixer0_out_tcon_top_mixer0: endpoint { > + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; > + }; > + }; > + }; > + }; > + > + mixer1: mixer@5200000 { > + compatible = "allwinner,sun20i-d1-de2-mixer-1"; > + reg = <0x5200000 0x100000>; > + clocks = <&display_clocks CLK_BUS_MIXER1>, > + <&display_clocks CLK_MIXER1>; > + clock-names = "bus", "mod"; > + resets = <&display_clocks RST_MIXER1>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mixer1_out: port@1 { > + reg = <1>; > + > + mixer1_out_tcon_top_mixer1: endpoint { > + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; > + }; > + }; > + }; > + }; > + > + tcon_top: tcon-top@5460000 { > + compatible = "allwinner,sun20i-d1-tcon-top"; > + reg = <0x5460000 0x1000>; > + clocks = <&ccu CLK_BUS_DPSS_TOP>, > + <&ccu CLK_TCON_TV>, > + <&ccu CLK_TVE>, > + <&ccu CLK_MIPI_DSI>; > + clock-names = "bus", "tcon-tv0", "tve0", "dsi"; > + clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; > + resets = <&ccu RST_BUS_DPSS_TOP>; > + #clock-cells = <1>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer0_in: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer0_in_mixer0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&mixer0_out_tcon_top_mixer0>; > + }; > + }; > + > + tcon_top_mixer0_out: port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; > + }; > + > + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { > + reg = <2>; > + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; > + }; > + }; > + > + tcon_top_mixer1_in: port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer1_in_mixer1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&mixer1_out_tcon_top_mixer1>; > + }; > + }; > + > + tcon_top_mixer1_out: port@3 { > + reg = <3>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; > + }; > + > + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { > + reg = <2>; > + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; > + }; > + }; > + > + tcon_top_hdmi_in: port@4 { > + reg = <4>; > + > + tcon_top_hdmi_in_tcon_tv0: endpoint { > + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; > + }; > + }; > + > + tcon_top_hdmi_out: port@5 { > + reg = <5>; > + }; > + }; > + }; > + > + tcon_lcd0: lcd-controller@5461000 { > + compatible = "allwinner,sun20i-d1-tcon-lcd"; > + reg = <0x5461000 0x1000>; > + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_TCON_LCD0>, > + <&ccu CLK_TCON_LCD0>; > + clock-names = "ahb", "tcon-ch0"; > + clock-output-names = "tcon-pixel-clock"; > + resets = <&ccu RST_BUS_TCON_LCD0>, > + <&ccu RST_BUS_LVDS0>; > + reset-names = "lcd", "lvds"; > + #clock-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_lcd0_in: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; > + }; > + > + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; > + }; > + }; > + > + tcon_lcd0_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > + tcon_tv0: lcd-controller@5470000 { > + compatible = "allwinner,sun20i-d1-tcon-tv"; > + reg = <0x5470000 0x1000>; > + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_TCON_TV>, > + <&tcon_top CLK_TCON_TOP_TV0>; > + clock-names = "ahb", "tcon-ch1"; > + resets = <&ccu RST_BUS_TCON_TV>; > + reset-names = "lcd"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_tv0_in: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; > + }; > + > + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; > + }; > + }; > + > + tcon_tv0_out: port@1 { > + reg = <1>; > + > + tcon_tv0_out_tcon_top_hdmi: endpoint { > + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; > + }; > + }; > + }; > + }; > + > + riscv_wdt: watchdog@6011000 { > + compatible = "allwinner,sun20i-d1-wdt"; > + reg = <0x6011000 0x20>; > + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>, <&rtc CLK_OSC32K>; > + clock-names = "hosc", "losc"; > + }; > + > + r_ccu: clock-controller@7010000 { > + compatible = "allwinner,sun20i-d1-r-ccu"; > + reg = <0x7010000 0x400>; > + clocks = <&osc24M>, > + <&rtc CLK_OSC32K>, > + <&rtc CLK_IOSC>, > + <&ccu CLK_PLL_PERIPH0_DIV3>; > + clock-names = "hosc", "losc", "iosc", "pll-periph"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + rtc: rtc@7090000 { > + compatible = "allwinner,sun20i-d1-rtc", > + "allwinner,sun50i-r329-rtc"; > + reg = <0x7090000 0x400>; > + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&r_ccu CLK_BUS_R_RTC>, > + <&osc24M>, > + <&r_ccu CLK_R_AHB>; > + clock-names = "bus", "hosc", "ahb"; > + #clock-cells = <1>; > + }; > + > + plic: interrupt-controller@10000000 { > + compatible = "allwinner,sun20i-d1-plic", > + "thead,c900-plic"; > + reg = <0x10000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, > + <&cpu0_intc 9>; > + interrupt-controller; > + riscv,ndev = <176>; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + }; > + }; > +};
On 15/08/2022 14:11, Andre Przywara wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Mon, 15 Aug 2022 00:08:09 -0500 > Samuel Holland <samuel@sholland.org> wrote: > > Hi, > > thanks for all the efforts in getting those SoC peripherals supported! > >> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as >> one HiFi 4 DSP. The SoC is based on a design that additionally contained >> a pair of Cortex A7's. For that reason, some peripherals are duplicated. > > So because of this, the Allwinner R528 and T113 SoCs would share almost > everything in this file. Would it be useful to already split this DT up? > To have a base .dtsi, basically this file without /cpus and /soc/plic, > then have a RISC-V specific file with just those, including the base? > There is precedence for this across-arch(-directories) sharing with the > Raspberry Pi and Allwinner H3/H5 SoCs. For those playing along at home, one example is the arm64 bananapi m2 dts which looks like: > /dts-v1/; > #include "sun50i-h5.dtsi" > #include "sun50i-h5-cpu-opp.dtsi" > #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi> > > / { > model = "Banana Pi BPI-M2-Plus v1.2 H5"; > compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5"; > }; I think this is a pretty good idea, and putting in the modularity up front seems logical to me, so when the arm one does eventually get added it can be done by only touching a single arch. Thanks, Conor. > > Or do you plan to leave that for when support for the ARM core versions is > actually submitted? But I don't think we need any extra *code* for that, > it's just the DT? > > Cheers, > Andre. > > >> >> This devicetree includes all of the peripherals that already have a >> documented binding. >> >> Signed-off-by: Samuel Holland <samuel@sholland.org> >> --- >> >> arch/riscv/boot/dts/Makefile | 1 + >> arch/riscv/boot/dts/allwinner/Makefile | 1 + >> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++ >> 3 files changed, 902 insertions(+) >> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile >> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi >> >> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile >> index ff174996cdfd..f292e31bdb2c 100644 >> --- a/arch/riscv/boot/dts/Makefile >> +++ b/arch/riscv/boot/dts/Makefile >> @@ -1,4 +1,5 @@ >> # SPDX-License-Identifier: GPL-2.0 >> +subdir-y += allwinner >> subdir-y += sifive >> subdir-y += starfive >> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan >> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile >> new file mode 100644 >> index 000000000000..f66554cd5c45 >> --- /dev/null >> +++ b/arch/riscv/boot/dts/allwinner/Makefile >> @@ -0,0 +1 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi >> new file mode 100644 >> index 000000000000..d1429274f22e >> --- /dev/null >> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi >> @@ -0,0 +1,900 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ or MIT) >> +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> >> + >> +#include <dt-bindings/clock/sun6i-rtc.h> >> +#include <dt-bindings/clock/sun8i-de2.h> >> +#include <dt-bindings/clock/sun8i-tcon-top.h> >> +#include <dt-bindings/clock/sun20i-d1-ccu.h> >> +#include <dt-bindings/clock/sun20i-d1-r-ccu.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/reset/sun8i-de2.h> >> +#include <dt-bindings/reset/sun20i-d1-ccu.h> >> +#include <dt-bindings/reset/sun20i-d1-r-ccu.h> >> +#include <dt-bindings/thermal/thermal.h> >> + >> +/ { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + cpus { >> + timebase-frequency = <24000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "thead,c906", "riscv"; >> + device_type = "cpu"; >> + reg = <0>; >> + clocks = <&ccu CLK_RISCV>; >> + clock-frequency = <24000000>; >> + d-cache-block-size = <64>; >> + d-cache-sets = <256>; >> + d-cache-size = <32768>; >> + i-cache-block-size = <64>; >> + i-cache-sets = <128>; >> + i-cache-size = <32768>; >> + mmu-type = "riscv,sv39"; >> + riscv,isa = "rv64imafdc"; >> + #cooling-cells = <2>; >> + >> + cpu0_intc: interrupt-controller { >> + compatible = "riscv,cpu-intc"; >> + interrupt-controller; >> + #address-cells = <0>; >> + #interrupt-cells = <1>; >> + }; >> + }; >> + }; >> + >> + de: display-engine { >> + compatible = "allwinner,sun20i-d1-display-engine"; >> + allwinner,pipelines = <&mixer0>, <&mixer1>; >> + status = "disabled"; >> + }; >> + >> + osc24M: osc24M-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "osc24M"; >> + #clock-cells = <0>; >> + }; >> + >> + soc { >> + compatible = "simple-bus"; >> + ranges; >> + interrupt-parent = <&plic>; >> + dma-noncoherent; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + dsp_wdt: watchdog@1700400 { >> + compatible = "allwinner,sun20i-d1-wdt"; >> + reg = <0x1700400 0x20>; >> + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&osc24M>, <&rtc CLK_OSC32K>; >> + clock-names = "hosc", "losc"; >> + status = "reserved"; >> + }; >> + >> + pio: pinctrl@2000000 { >> + compatible = "allwinner,sun20i-d1-pinctrl"; >> + reg = <0x2000000 0x800>; >> + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>, >> + <87 IRQ_TYPE_LEVEL_HIGH>, >> + <89 IRQ_TYPE_LEVEL_HIGH>, >> + <91 IRQ_TYPE_LEVEL_HIGH>, >> + <93 IRQ_TYPE_LEVEL_HIGH>, >> + <95 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_APB0>, >> + <&osc24M>, >> + <&rtc CLK_OSC32K>; >> + clock-names = "apb", "hosc", "losc"; >> + gpio-controller; >> + interrupt-controller; >> + #gpio-cells = <3>; >> + #interrupt-cells = <3>; >> + >> + /omit-if-no-ref/ >> + i2c0_pb10_pins: i2c0-pb10-pins { >> + pins = "PB10", "PB11"; >> + function = "i2c0"; >> + }; >> + >> + /omit-if-no-ref/ >> + i2c2_pb0_pins: i2c2-pb0-pins { >> + pins = "PB0", "PB1"; >> + function = "i2c2"; >> + }; >> + >> + /omit-if-no-ref/ >> + lcd_rgb666_pins: lcd-rgb666-pins { >> + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", >> + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", >> + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", >> + "PD18", "PD19", "PD20", "PD21"; >> + function = "lcd0"; >> + }; >> + >> + /omit-if-no-ref/ >> + mmc0_pins: mmc0-pins { >> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; >> + function = "mmc0"; >> + }; >> + >> + /omit-if-no-ref/ >> + mmc1_pins: mmc1-pins { >> + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; >> + function = "mmc1"; >> + }; >> + >> + /omit-if-no-ref/ >> + mmc2_pins: mmc2-pins { >> + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; >> + function = "mmc2"; >> + }; >> + >> + /omit-if-no-ref/ >> + rgmii_pe_pins: rgmii-pe-pins { >> + pins = "PE0", "PE1", "PE2", "PE3", "PE4", >> + "PE5", "PE6", "PE7", "PE8", "PE9", >> + "PE11", "PE12", "PE13", "PE14", "PE15"; >> + function = "emac"; >> + }; >> + >> + /omit-if-no-ref/ >> + rmii_pe_pins: rmii-pe-pins { >> + pins = "PE0", "PE1", "PE2", "PE3", "PE4", >> + "PE5", "PE6", "PE7", "PE8", "PE9"; >> + function = "emac"; >> + }; >> + >> + /omit-if-no-ref/ >> + uart0_pb8_pins: uart0-pb8-pins { >> + pins = "PB8", "PB9"; >> + function = "uart0"; >> + }; >> + >> + /omit-if-no-ref/ >> + uart1_pg6_pins: uart1-pg6-pins { >> + pins = "PG6", "PG7"; >> + function = "uart1"; >> + }; >> + >> + /omit-if-no-ref/ >> + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { >> + pins = "PG8", "PG9"; >> + function = "uart1"; >> + }; >> + }; >> + >> + ccu: clock-controller@2001000 { >> + compatible = "allwinner,sun20i-d1-ccu"; >> + reg = <0x2001000 0x1000>; >> + clocks = <&osc24M>, >> + <&rtc CLK_OSC32K>, >> + <&rtc CLK_IOSC>; >> + clock-names = "hosc", "losc", "iosc"; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> + lradc: keys@2009800 { >> + compatible = "allwinner,sun20i-d1-lradc", >> + "allwinner,sun50i-r329-lradc"; >> + reg = <0x2009800 0x400>; >> + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_LRADC>; >> + resets = <&ccu RST_BUS_LRADC>; >> + status = "disabled"; >> + }; >> + >> + codec: audio-codec@2030000 { >> + compatible = "simple-mfd", "syscon"; >> + reg = <0x2030000 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + regulators@2030348 { >> + compatible = "allwinner,sun20i-d1-analog-ldos"; >> + reg = <0x2030348 0x4>; >> + nvmem-cells = <&bg_trim>; >> + nvmem-cell-names = "bg_trim"; >> + >> + reg_aldo: aldo { >> + }; >> + >> + reg_hpldo: hpldo { >> + }; >> + }; >> + }; >> + >> + i2s0: i2s@2032000 { >> + compatible = "allwinner,sun20i-d1-i2s", >> + "allwinner,sun50i-r329-i2s"; >> + reg = <0x2032000 0x1000>; >> + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_I2S0>, >> + <&ccu CLK_I2S0>; >> + clock-names = "apb", "mod"; >> + resets = <&ccu RST_BUS_I2S0>; >> + dmas = <&dma 3>, <&dma 3>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + #sound-dai-cells = <0>; >> + }; >> + >> + i2s1: i2s@2033000 { >> + compatible = "allwinner,sun20i-d1-i2s", >> + "allwinner,sun50i-r329-i2s"; >> + reg = <0x2033000 0x1000>; >> + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_I2S1>, >> + <&ccu CLK_I2S1>; >> + clock-names = "apb", "mod"; >> + resets = <&ccu RST_BUS_I2S1>; >> + dmas = <&dma 4>, <&dma 4>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + #sound-dai-cells = <0>; >> + }; >> + >> + i2s2: i2s@2034000 { >> + compatible = "allwinner,sun20i-d1-i2s", >> + "allwinner,sun50i-r329-i2s"; >> + reg = <0x2034000 0x1000>; >> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_I2S2>, >> + <&ccu CLK_I2S2>; >> + clock-names = "apb", "mod"; >> + resets = <&ccu RST_BUS_I2S2>; >> + dmas = <&dma 5>, <&dma 5>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + #sound-dai-cells = <0>; >> + }; >> + >> + timer: timer@2050000 { >> + compatible = "allwinner,sun20i-d1-timer", >> + "allwinner,sun8i-a23-timer"; >> + reg = <0x2050000 0xa0>; >> + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>, >> + <76 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&osc24M>; >> + }; >> + >> + wdt: watchdog@20500a0 { >> + compatible = "allwinner,sun20i-d1-wdt-reset", >> + "allwinner,sun20i-d1-wdt"; >> + reg = <0x20500a0 0x20>; >> + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&osc24M>, <&rtc CLK_OSC32K>; >> + clock-names = "hosc", "losc"; >> + status = "reserved"; >> + }; >> + >> + uart0: serial@2500000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x2500000 0x400>; >> + reg-io-width = <4>; >> + reg-shift = <2>; >> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_UART0>; >> + resets = <&ccu RST_BUS_UART0>; >> + dmas = <&dma 14>, <&dma 14>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + uart1: serial@2500400 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x2500400 0x400>; >> + reg-io-width = <4>; >> + reg-shift = <2>; >> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_UART1>; >> + resets = <&ccu RST_BUS_UART1>; >> + dmas = <&dma 15>, <&dma 15>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + uart2: serial@2500800 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x2500800 0x400>; >> + reg-io-width = <4>; >> + reg-shift = <2>; >> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_UART2>; >> + resets = <&ccu RST_BUS_UART2>; >> + dmas = <&dma 16>, <&dma 16>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + uart3: serial@2500c00 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x2500c00 0x400>; >> + reg-io-width = <4>; >> + reg-shift = <2>; >> + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_UART3>; >> + resets = <&ccu RST_BUS_UART3>; >> + dmas = <&dma 17>, <&dma 17>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + uart4: serial@2501000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x2501000 0x400>; >> + reg-io-width = <4>; >> + reg-shift = <2>; >> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_UART4>; >> + resets = <&ccu RST_BUS_UART4>; >> + dmas = <&dma 18>, <&dma 18>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + uart5: serial@2501400 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x2501400 0x400>; >> + reg-io-width = <4>; >> + reg-shift = <2>; >> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_UART5>; >> + resets = <&ccu RST_BUS_UART5>; >> + dmas = <&dma 19>, <&dma 19>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + i2c0: i2c@2502000 { >> + compatible = "allwinner,sun20i-d1-i2c", >> + "allwinner,sun8i-v536-i2c", >> + "allwinner,sun6i-a31-i2c"; >> + reg = <0x2502000 0x400>; >> + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_I2C0>; >> + resets = <&ccu RST_BUS_I2C0>; >> + dmas = <&dma 43>, <&dma 43>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + i2c1: i2c@2502400 { >> + compatible = "allwinner,sun20i-d1-i2c", >> + "allwinner,sun8i-v536-i2c", >> + "allwinner,sun6i-a31-i2c"; >> + reg = <0x2502400 0x400>; >> + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_I2C1>; >> + resets = <&ccu RST_BUS_I2C1>; >> + dmas = <&dma 44>, <&dma 44>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + i2c2: i2c@2502800 { >> + compatible = "allwinner,sun20i-d1-i2c", >> + "allwinner,sun8i-v536-i2c", >> + "allwinner,sun6i-a31-i2c"; >> + reg = <0x2502800 0x400>; >> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_I2C2>; >> + resets = <&ccu RST_BUS_I2C2>; >> + dmas = <&dma 45>, <&dma 45>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + i2c3: i2c@2502c00 { >> + compatible = "allwinner,sun20i-d1-i2c", >> + "allwinner,sun8i-v536-i2c", >> + "allwinner,sun6i-a31-i2c"; >> + reg = <0x2502c00 0x400>; >> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_I2C3>; >> + resets = <&ccu RST_BUS_I2C3>; >> + dmas = <&dma 46>, <&dma 46>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + syscon: syscon@3000000 { >> + compatible = "allwinner,sun20i-d1-system-control"; >> + reg = <0x3000000 0x1000>; >> + ranges; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + regulators@3000150 { >> + compatible = "allwinner,sun20i-d1-system-ldos"; >> + reg = <0x3000150 0x4>; >> + >> + reg_ldoa: ldoa { >> + }; >> + >> + reg_ldob: ldob { >> + }; >> + }; >> + }; >> + >> + dma: dma-controller@3002000 { >> + compatible = "allwinner,sun20i-d1-dma"; >> + reg = <0x3002000 0x1000>; >> + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; >> + clock-names = "bus", "mbus"; >> + resets = <&ccu RST_BUS_DMA>; >> + dma-channels = <16>; >> + dma-requests = <48>; >> + #dma-cells = <1>; >> + }; >> + >> + sid: efuse@3006000 { >> + compatible = "allwinner,sun20i-d1-sid"; >> + reg = <0x3006000 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + ths_calib: ths-calib@14 { >> + reg = <0x14 0x4>; >> + }; >> + >> + bg_trim: bg-trim@28 { >> + reg = <0x28 0x4>; >> + bits = <16 8>; >> + }; >> + }; >> + >> + mbus: dram-controller@3102000 { >> + compatible = "allwinner,sun20i-d1-mbus"; >> + reg = <0x3102000 0x1000>, >> + <0x3103000 0x1000>; >> + reg-names = "mbus", "dram"; >> + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_MBUS>, >> + <&ccu CLK_DRAM>, >> + <&ccu CLK_BUS_DRAM>; >> + clock-names = "mbus", "dram", "bus"; >> + dma-ranges = <0 0x40000000 0x80000000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + #interconnect-cells = <1>; >> + }; >> + >> + mmc0: mmc@4020000 { >> + compatible = "allwinner,sun20i-d1-mmc"; >> + reg = <0x4020000 0x1000>; >> + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; >> + clock-names = "ahb", "mmc"; >> + resets = <&ccu RST_BUS_MMC0>; >> + reset-names = "ahb"; >> + cap-sd-highspeed; >> + max-frequency = <150000000>; >> + no-mmc; >> + status = "disabled"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + mmc1: mmc@4021000 { >> + compatible = "allwinner,sun20i-d1-mmc"; >> + reg = <0x4021000 0x1000>; >> + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; >> + clock-names = "ahb", "mmc"; >> + resets = <&ccu RST_BUS_MMC1>; >> + reset-names = "ahb"; >> + cap-sd-highspeed; >> + max-frequency = <150000000>; >> + no-mmc; >> + status = "disabled"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + mmc2: mmc@4022000 { >> + compatible = "allwinner,sun20i-d1-emmc", >> + "allwinner,sun50i-a100-emmc"; >> + reg = <0x4022000 0x1000>; >> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; >> + clock-names = "ahb", "mmc"; >> + resets = <&ccu RST_BUS_MMC2>; >> + reset-names = "ahb"; >> + cap-mmc-highspeed; >> + max-frequency = <150000000>; >> + mmc-ddr-1_8v; >> + mmc-ddr-3_3v; >> + no-sd; >> + no-sdio; >> + status = "disabled"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + usb_otg: usb@4100000 { >> + compatible = "allwinner,sun20i-d1-musb", >> + "allwinner,sun8i-a33-musb"; >> + reg = <0x4100000 0x400>; >> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "mc"; >> + clocks = <&ccu CLK_BUS_OTG>; >> + resets = <&ccu RST_BUS_OTG>; >> + extcon = <&usbphy 0>; >> + phys = <&usbphy 0>; >> + phy-names = "usb"; >> + status = "disabled"; >> + }; >> + >> + usbphy: phy@4100400 { >> + compatible = "allwinner,sun20i-d1-usb-phy"; >> + reg = <0x4100400 0x100>, >> + <0x4101800 0x100>, >> + <0x4200800 0x100>; >> + reg-names = "phy_ctrl", >> + "pmu0", >> + "pmu1"; >> + clocks = <&osc24M>, >> + <&osc24M>; >> + clock-names = "usb0_phy", >> + "usb1_phy"; >> + resets = <&ccu RST_USB_PHY0>, >> + <&ccu RST_USB_PHY1>; >> + reset-names = "usb0_reset", >> + "usb1_reset"; >> + status = "disabled"; >> + #phy-cells = <1>; >> + }; >> + >> + ehci0: usb@4101000 { >> + compatible = "allwinner,sun20i-d1-ehci", >> + "generic-ehci"; >> + reg = <0x4101000 0x100>; >> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI0>, >> + <&ccu CLK_BUS_EHCI0>, >> + <&ccu CLK_USB_OHCI0>; >> + resets = <&ccu RST_BUS_OHCI0>, >> + <&ccu RST_BUS_EHCI0>; >> + phys = <&usbphy 0>; >> + phy-names = "usb"; >> + status = "disabled"; >> + }; >> + >> + ohci0: usb@4101400 { >> + compatible = "allwinner,sun20i-d1-ohci", >> + "generic-ohci"; >> + reg = <0x4101400 0x100>; >> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI0>, >> + <&ccu CLK_USB_OHCI0>; >> + resets = <&ccu RST_BUS_OHCI0>; >> + phys = <&usbphy 0>; >> + phy-names = "usb"; >> + status = "disabled"; >> + }; >> + >> + ehci1: usb@4200000 { >> + compatible = "allwinner,sun20i-d1-ehci", >> + "generic-ehci"; >> + reg = <0x4200000 0x100>; >> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI1>, >> + <&ccu CLK_BUS_EHCI1>, >> + <&ccu CLK_USB_OHCI1>; >> + resets = <&ccu RST_BUS_OHCI1>, >> + <&ccu RST_BUS_EHCI1>; >> + phys = <&usbphy 1>; >> + phy-names = "usb"; >> + status = "disabled"; >> + }; >> + >> + ohci1: usb@4200400 { >> + compatible = "allwinner,sun20i-d1-ohci", >> + "generic-ohci"; >> + reg = <0x4200400 0x100>; >> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI1>, >> + <&ccu CLK_USB_OHCI1>; >> + resets = <&ccu RST_BUS_OHCI1>; >> + phys = <&usbphy 1>; >> + phy-names = "usb"; >> + status = "disabled"; >> + }; >> + >> + emac: ethernet@4500000 { >> + compatible = "allwinner,sun20i-d1-emac", >> + "allwinner,sun50i-a64-emac"; >> + reg = <0x4500000 0x10000>; >> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "macirq"; >> + clocks = <&ccu CLK_BUS_EMAC>; >> + clock-names = "stmmaceth"; >> + resets = <&ccu RST_BUS_EMAC>; >> + reset-names = "stmmaceth"; >> + syscon = <&syscon>; >> + status = "disabled"; >> + >> + mdio: mdio { >> + compatible = "snps,dwmac-mdio"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + >> + display_clocks: clock-controller@5000000 { >> + compatible = "allwinner,sun20i-d1-de2-clk", >> + "allwinner,sun50i-h5-de2-clk"; >> + reg = <0x5000000 0x10000>; >> + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; >> + clock-names = "bus", "mod"; >> + resets = <&ccu RST_BUS_DE>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> + mixer0: mixer@5100000 { >> + compatible = "allwinner,sun20i-d1-de2-mixer-0"; >> + reg = <0x5100000 0x100000>; >> + clocks = <&display_clocks CLK_BUS_MIXER0>, >> + <&display_clocks CLK_MIXER0>; >> + clock-names = "bus", "mod"; >> + resets = <&display_clocks RST_MIXER0>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + mixer0_out: port@1 { >> + reg = <1>; >> + >> + mixer0_out_tcon_top_mixer0: endpoint { >> + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; >> + }; >> + }; >> + }; >> + }; >> + >> + mixer1: mixer@5200000 { >> + compatible = "allwinner,sun20i-d1-de2-mixer-1"; >> + reg = <0x5200000 0x100000>; >> + clocks = <&display_clocks CLK_BUS_MIXER1>, >> + <&display_clocks CLK_MIXER1>; >> + clock-names = "bus", "mod"; >> + resets = <&display_clocks RST_MIXER1>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + mixer1_out: port@1 { >> + reg = <1>; >> + >> + mixer1_out_tcon_top_mixer1: endpoint { >> + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; >> + }; >> + }; >> + }; >> + }; >> + >> + tcon_top: tcon-top@5460000 { >> + compatible = "allwinner,sun20i-d1-tcon-top"; >> + reg = <0x5460000 0x1000>; >> + clocks = <&ccu CLK_BUS_DPSS_TOP>, >> + <&ccu CLK_TCON_TV>, >> + <&ccu CLK_TVE>, >> + <&ccu CLK_MIPI_DSI>; >> + clock-names = "bus", "tcon-tv0", "tve0", "dsi"; >> + clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; >> + resets = <&ccu RST_BUS_DPSS_TOP>; >> + #clock-cells = <1>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_top_mixer0_in: port@0 { >> + reg = <0>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_top_mixer0_in_mixer0: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&mixer0_out_tcon_top_mixer0>; >> + }; >> + }; >> + >> + tcon_top_mixer0_out: port@1 { >> + reg = <1>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; >> + }; >> + >> + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { >> + reg = <2>; >> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; >> + }; >> + }; >> + >> + tcon_top_mixer1_in: port@2 { >> + reg = <2>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_top_mixer1_in_mixer1: endpoint@1 { >> + reg = <1>; >> + remote-endpoint = <&mixer1_out_tcon_top_mixer1>; >> + }; >> + }; >> + >> + tcon_top_mixer1_out: port@3 { >> + reg = <3>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; >> + }; >> + >> + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { >> + reg = <2>; >> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; >> + }; >> + }; >> + >> + tcon_top_hdmi_in: port@4 { >> + reg = <4>; >> + >> + tcon_top_hdmi_in_tcon_tv0: endpoint { >> + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; >> + }; >> + }; >> + >> + tcon_top_hdmi_out: port@5 { >> + reg = <5>; >> + }; >> + }; >> + }; >> + >> + tcon_lcd0: lcd-controller@5461000 { >> + compatible = "allwinner,sun20i-d1-tcon-lcd"; >> + reg = <0x5461000 0x1000>; >> + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_TCON_LCD0>, >> + <&ccu CLK_TCON_LCD0>; >> + clock-names = "ahb", "tcon-ch0"; >> + clock-output-names = "tcon-pixel-clock"; >> + resets = <&ccu RST_BUS_TCON_LCD0>, >> + <&ccu RST_BUS_LVDS0>; >> + reset-names = "lcd", "lvds"; >> + #clock-cells = <0>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_lcd0_in: port@0 { >> + reg = <0>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; >> + }; >> + >> + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { >> + reg = <1>; >> + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; >> + }; >> + }; >> + >> + tcon_lcd0_out: port@1 { >> + reg = <1>; >> + }; >> + }; >> + }; >> + >> + tcon_tv0: lcd-controller@5470000 { >> + compatible = "allwinner,sun20i-d1-tcon-tv"; >> + reg = <0x5470000 0x1000>; >> + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_TCON_TV>, >> + <&tcon_top CLK_TCON_TOP_TV0>; >> + clock-names = "ahb", "tcon-ch1"; >> + resets = <&ccu RST_BUS_TCON_TV>; >> + reset-names = "lcd"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_tv0_in: port@0 { >> + reg = <0>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; >> + }; >> + >> + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { >> + reg = <1>; >> + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; >> + }; >> + }; >> + >> + tcon_tv0_out: port@1 { >> + reg = <1>; >> + >> + tcon_tv0_out_tcon_top_hdmi: endpoint { >> + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; >> + }; >> + }; >> + }; >> + }; >> + >> + riscv_wdt: watchdog@6011000 { >> + compatible = "allwinner,sun20i-d1-wdt"; >> + reg = <0x6011000 0x20>; >> + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&osc24M>, <&rtc CLK_OSC32K>; >> + clock-names = "hosc", "losc"; >> + }; >> + >> + r_ccu: clock-controller@7010000 { >> + compatible = "allwinner,sun20i-d1-r-ccu"; >> + reg = <0x7010000 0x400>; >> + clocks = <&osc24M>, >> + <&rtc CLK_OSC32K>, >> + <&rtc CLK_IOSC>, >> + <&ccu CLK_PLL_PERIPH0_DIV3>; >> + clock-names = "hosc", "losc", "iosc", "pll-periph"; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> + rtc: rtc@7090000 { >> + compatible = "allwinner,sun20i-d1-rtc", >> + "allwinner,sun50i-r329-rtc"; >> + reg = <0x7090000 0x400>; >> + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&r_ccu CLK_BUS_R_RTC>, >> + <&osc24M>, >> + <&r_ccu CLK_R_AHB>; >> + clock-names = "bus", "hosc", "ahb"; >> + #clock-cells = <1>; >> + }; >> + >> + plic: interrupt-controller@10000000 { >> + compatible = "allwinner,sun20i-d1-plic", >> + "thead,c900-plic"; >> + reg = <0x10000000 0x4000000>; >> + interrupts-extended = <&cpu0_intc 11>, >> + <&cpu0_intc 9>; >> + interrupt-controller; >> + riscv,ndev = <176>; >> + #address-cells = <0>; >> + #interrupt-cells = <2>; >> + }; >> + }; >> +}; >
On 15/08/2022 08:08, Samuel Holland wrote: > + > + de: display-engine { > + compatible = "allwinner,sun20i-d1-display-engine"; > + allwinner,pipelines = <&mixer0>, <&mixer1>; > + status = "disabled"; > + }; > + > + osc24M: osc24M-clk { lowercase > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; This is a property of the board, not SoC. > + clock-output-names = "osc24M"; > + #clock-cells = <0>; > + }; > + Best regards, Krzysztof
Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski napisal(a): > On 15/08/2022 08:08, Samuel Holland wrote: > > + > > + de: display-engine { > > + compatible = "allwinner,sun20i-d1-display-engine"; > > + allwinner,pipelines = <&mixer0>, <&mixer1>; > > + status = "disabled"; > > + }; > > + > > + osc24M: osc24M-clk { > > lowercase > > > + compatible = "fixed-clock"; > > + clock-frequency = <24000000>; > > This is a property of the board, not SoC. SoC needs 24 MHz oscillator for correct operation, so each and every board has it. Having it here simplifies board DT files. Best regards, Jernej > > > + clock-output-names = "osc24M"; > > + #clock-cells = <0>; > > + }; > > + > > Best regards, > Krzysztof
Am Montag, 15. August 2022, 07:08:09 CEST schrieb Samuel Holland: > D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as > one HiFi 4 DSP. The SoC is based on a design that additionally contained > a pair of Cortex A7's. For that reason, some peripherals are duplicated. > > This devicetree includes all of the peripherals that already have a > documented binding. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Tested-by: Heiko Stuebner <heiko@sntech.de>
Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec: > Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski napisal(a): > > On 15/08/2022 08:08, Samuel Holland wrote: > > > + > > > + de: display-engine { > > > + compatible = "allwinner,sun20i-d1-display-engine"; > > > + allwinner,pipelines = <&mixer0>, <&mixer1>; > > > + status = "disabled"; > > > + }; > > > + > > > + osc24M: osc24M-clk { > > > > lowercase > > > > > + compatible = "fixed-clock"; > > > + clock-frequency = <24000000>; > > > > This is a property of the board, not SoC. > > SoC needs 24 MHz oscillator for correct operation, so each and every board has > it. Having it here simplifies board DT files. I guess the oscillator is a separate component on each board, right? And DT obvious is meant to describe the hardware - independently from implementation-specific choices. Starting to discuss which exceptions to allow then might lead to even more exceptions. Also having to look for a board-component in the soc dtsi also is surprising if one gets to the party later on :-) .
Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a): > Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec: > > Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski napisal(a): > > > On 15/08/2022 08:08, Samuel Holland wrote: > > > > + > > > > + de: display-engine { > > > > + compatible = "allwinner,sun20i-d1-display-engine"; > > > > + allwinner,pipelines = <&mixer0>, <&mixer1>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + osc24M: osc24M-clk { > > > > > > lowercase > > > > > > > + compatible = "fixed-clock"; > > > > + clock-frequency = <24000000>; > > > > > > This is a property of the board, not SoC. > > > > SoC needs 24 MHz oscillator for correct operation, so each and every board > > has it. Having it here simplifies board DT files. > > I guess the oscillator is a separate component on each board, right? Correct. > And DT obvious is meant to describe the hardware - independently from > implementation-specific choices. There is no choice in this case. 24 MHz crystal has to be present. FWIW, including crystal node in SoC specific DTSI is already common pattern in Allwinner ARM SoC DTSI files. > > Starting to discuss which exceptions to allow then might lead to even more > exceptions. > > Also having to look for a board-component in the soc dtsi also is surprising > if one gets to the party later on :-) . As I said, if one is accustomed to Allwinner ARM DT development, it would be more surprising to include 24 MHz crystal node in each and every board DT. Best regards, Jernej
On 16/08/2022 12:25, Jernej Škrabec wrote: > Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a): >> Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec: >>> Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski > napisal(a): >>>> On 15/08/2022 08:08, Samuel Holland wrote: >>>>> + >>>>> + de: display-engine { >>>>> + compatible = "allwinner,sun20i-d1-display-engine"; >>>>> + allwinner,pipelines = <&mixer0>, <&mixer1>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + osc24M: osc24M-clk { >>>> >>>> lowercase >>>> >>>>> + compatible = "fixed-clock"; >>>>> + clock-frequency = <24000000>; >>>> >>>> This is a property of the board, not SoC. >>> >>> SoC needs 24 MHz oscillator for correct operation, so each and every board >>> has it. Having it here simplifies board DT files. >> >> I guess the oscillator is a separate component on each board, right? > > Correct. > >> And DT obvious is meant to describe the hardware - independently from >> implementation-specific choices. > > There is no choice in this case. 24 MHz crystal has to be present. > > FWIW, including crystal node in SoC specific DTSI is already common pattern in > Allwinner ARM SoC DTSI files. > >> >> Starting to discuss which exceptions to allow then might lead to even more >> exceptions. >> >> Also having to look for a board-component in the soc dtsi also is surprising >> if one gets to the party later on :-) . > > As I said, if one is accustomed to Allwinner ARM DT development, it would be > more surprising to include 24 MHz crystal node in each and every board DT. It's same everywhere. Allwinner, Exynos, iMX, Qualcomm. Everywhere this is a part of the board, so even if oscillator frequency is fixed (as in 99% of cases although some SoCs I think might just allow to implement one of few), still this is a property of the board. Because: 1. DTSI describes the SoC part, not board. 2. So the DTS developer is a bit more conscious about his design. Keeping things in SoC DTSI just because it simplifies DTS is not correct IMHO. So again - like in several other cases - minimum the frequency is property of the board, not the SoC DTSI. Everywhere. Allwinner is not special to receive exceptions. Best regards, Krzysztof
On Tue, 16 Aug 2022 12:42:39 +0300 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: Hi, > On 16/08/2022 12:25, Jernej Škrabec wrote: > > Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a): > >> Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec: > >>> Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski > > napisal(a): > >>>> On 15/08/2022 08:08, Samuel Holland wrote: > >>>>> + > >>>>> + de: display-engine { > >>>>> + compatible = "allwinner,sun20i-d1-display-engine"; > >>>>> + allwinner,pipelines = <&mixer0>, <&mixer1>; > >>>>> + status = "disabled"; > >>>>> + }; > >>>>> + > >>>>> + osc24M: osc24M-clk { > >>>> > >>>> lowercase > >>>> > >>>>> + compatible = "fixed-clock"; > >>>>> + clock-frequency = <24000000>; > >>>> > >>>> This is a property of the board, not SoC. > >>> > >>> SoC needs 24 MHz oscillator for correct operation, so each and every board > >>> has it. Having it here simplifies board DT files. > >> > >> I guess the oscillator is a separate component on each board, right? > > > > Correct. > > > >> And DT obvious is meant to describe the hardware - independently from > >> implementation-specific choices. > > > > There is no choice in this case. 24 MHz crystal has to be present. > > > > FWIW, including crystal node in SoC specific DTSI is already common pattern in > > Allwinner ARM SoC DTSI files. > > > >> > >> Starting to discuss which exceptions to allow then might lead to even more > >> exceptions. > >> > >> Also having to look for a board-component in the soc dtsi also is surprising > >> if one gets to the party later on :-) . > > > > As I said, if one is accustomed to Allwinner ARM DT development, it would be > > more surprising to include 24 MHz crystal node in each and every board DT. > > It's same everywhere. Allwinner, Exynos, iMX, Qualcomm. Everywhere this > is a part of the board, so even if oscillator frequency is fixed (as in > 99% of cases although some SoCs I think might just allow to implement > one of few), still this is a property of the board. Because: > 1. DTSI describes the SoC part, not board. > 2. So the DTS developer is a bit more conscious about his design. 1) is certainly true, but indeed most platforms put the base crystal oscillator in the SoC .dtsi: I just sampled Rockchip (rk3399.dtsi, rk356x.dtsi, rk3328.dtsi), Amlogic (meson-g12-common.dtsi), ActionSemi (s[79]00.dtsi), Qualcomm (msm8916.dtsi, sm8450.dtsi, sc7180.dtsi), Freescale (imx8mm.dtsi, imx8qxp.dtsi), Realtek (rtd129x.dtsi), Broadcom (bcm283x.dtsi), Mediatek (mt8183.dtsi, mt8516.dtsi). The list probably goes on (I just stopped here). I think one reason might be that this is so central to the whole SoC operation, that it's already referenced multiple times in the base .dtsi. And having a yet unresolved reference in the .dtsi looks dodgy. NVidia seems to omit a base oscillator (maybe it's implicit in their binding design), Marvell doesn't use a fixed-clock (but still puts their base clock in armada-37xx.dtsi). Exynos and Renesas put a *stub* fixed-clock in the .dtsi, and set the frequency in the board .dts files. Would this be a compromise? Cheers, Andre > Keeping things in SoC DTSI just because it simplifies DTS is not correct > IMHO. So again - like in several other cases - minimum the frequency is > property of the board, not the SoC DTSI. > > Everywhere. Allwinner is not special to receive exceptions. > > Best regards, > Krzysztof >
On 16/08/2022 14:00, Andre Przywara wrote: > On Tue, 16 Aug 2022 12:42:39 +0300 > Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > Hi, > >> On 16/08/2022 12:25, Jernej Škrabec wrote: >>> Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a): >>>> Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec: >>>>> Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski >>> napisal(a): >>>>>> On 15/08/2022 08:08, Samuel Holland wrote: >>>>>>> + >>>>>>> + de: display-engine { >>>>>>> + compatible = "allwinner,sun20i-d1-display-engine"; >>>>>>> + allwinner,pipelines = <&mixer0>, <&mixer1>; >>>>>>> + status = "disabled"; >>>>>>> + }; >>>>>>> + >>>>>>> + osc24M: osc24M-clk { >>>>>> >>>>>> lowercase >>>>>> >>>>>>> + compatible = "fixed-clock"; >>>>>>> + clock-frequency = <24000000>; >>>>>> >>>>>> This is a property of the board, not SoC. >>>>> >>>>> SoC needs 24 MHz oscillator for correct operation, so each and every board >>>>> has it. Having it here simplifies board DT files. >>>> >>>> I guess the oscillator is a separate component on each board, right? >>> >>> Correct. >>> >>>> And DT obvious is meant to describe the hardware - independently from >>>> implementation-specific choices. >>> >>> There is no choice in this case. 24 MHz crystal has to be present. >>> >>> FWIW, including crystal node in SoC specific DTSI is already common pattern in >>> Allwinner ARM SoC DTSI files. >>> >>>> >>>> Starting to discuss which exceptions to allow then might lead to even more >>>> exceptions. >>>> >>>> Also having to look for a board-component in the soc dtsi also is surprising >>>> if one gets to the party later on :-) . >>> >>> As I said, if one is accustomed to Allwinner ARM DT development, it would be >>> more surprising to include 24 MHz crystal node in each and every board DT. >> >> It's same everywhere. Allwinner, Exynos, iMX, Qualcomm. Everywhere this >> is a part of the board, so even if oscillator frequency is fixed (as in >> 99% of cases although some SoCs I think might just allow to implement >> one of few), still this is a property of the board. Because: >> 1. DTSI describes the SoC part, not board. >> 2. So the DTS developer is a bit more conscious about his design. > > 1) is certainly true, but indeed most platforms put the base > crystal oscillator in the SoC .dtsi: Yes. And once per week when I look at new DTS I need to repeat the same arguments. :) > I just sampled Rockchip (rk3399.dtsi, > rk356x.dtsi, rk3328.dtsi), Amlogic (meson-g12-common.dtsi), ActionSemi (s[79]00.dtsi), > Qualcomm (msm8916.dtsi, sm8450.dtsi, sc7180.dtsi), Freescale (imx8mm.dtsi, > imx8qxp.dtsi), Realtek (rtd129x.dtsi), Broadcom (bcm283x.dtsi), Mediatek > (mt8183.dtsi, mt8516.dtsi). The list probably goes on (I just stopped > here). > > I think one reason might be that this is so central to the whole SoC > operation, that it's already referenced multiple times in the base .dtsi. > And having a yet unresolved reference in the .dtsi looks dodgy. > > NVidia seems to omit a base oscillator (maybe it's implicit in their > binding design), Marvell doesn't use a fixed-clock (but still puts their > base clock in armada-37xx.dtsi). > > Exynos and Renesas put a *stub* fixed-clock in the .dtsi, and set the > frequency in the board .dts files. Would this be a compromise? This is exactly what I said before. The clock frequency is a property of the board. Feel free to keep the rest of the clock in the SoC DTSI to reduce duplication, but at minimum the clock should go to the board. Best regards, Krzysztof
On 16/08/2022 14:11, Krzysztof Kozlowski wrote: >> >> I think one reason might be that this is so central to the whole SoC >> operation, that it's already referenced multiple times in the base .dtsi. >> And having a yet unresolved reference in the .dtsi looks dodgy. >> >> NVidia seems to omit a base oscillator (maybe it's implicit in their >> binding design), Marvell doesn't use a fixed-clock (but still puts their >> base clock in armada-37xx.dtsi). >> >> Exynos and Renesas put a *stub* fixed-clock in the .dtsi, and set the >> frequency in the board .dts files. Would this be a compromise? > > This is exactly what I said before. The clock frequency is a property of > the board. Feel free to keep the rest of the clock in the SoC DTSI to > reduce duplication, but at minimum the clock should go to the board. s/minimum the clock should go to the board/minimum the clock frequency should go to the board./ Best regards, Krzysztof
On 16/08/2022 12:12, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 16/08/2022 14:11, Krzysztof Kozlowski wrote: >>> >>> I think one reason might be that this is so central to the whole SoC >>> operation, that it's already referenced multiple times in the base .dtsi. >>> And having a yet unresolved reference in the .dtsi looks dodgy. >>> >>> NVidia seems to omit a base oscillator (maybe it's implicit in their >>> binding design), Marvell doesn't use a fixed-clock (but still puts their >>> base clock in armada-37xx.dtsi). >>> >>> Exynos and Renesas put a *stub* fixed-clock in the .dtsi, and set the >>> frequency in the board .dts files. Would this be a compromise? >> >> This is exactly what I said before. The clock frequency is a property of >> the board. Feel free to keep the rest of the clock in the SoC DTSI to >> reduce duplication, but at minimum the clock should go to the board. > > > s/minimum the clock should go to the board/minimum the clock frequency > should go to the board./ FWIW this is what the PolarFire SoC stuff does (thanks to either yourself or Geert) & it'd be nice to continue that precedence for riscv dts going forward. No point IMO in duplicating things done in the past in arch/arm if that's now considered bad practice.
On 15/08/2022 08:08, Samuel Holland wrote: > D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as > one HiFi 4 DSP. The SoC is based on a design that additionally contained > a pair of Cortex A7's. For that reason, some peripherals are duplicated. > > This devicetree includes all of the peripherals that already have a > documented binding. > > Signed-off-by: Samuel Holland <samuel@sholland.org> (...) > + > + codec: audio-codec@2030000 { > + compatible = "simple-mfd", "syscon"; This alone is not correct. You must use device specific compatible. > + reg = <0x2030000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + regulators@2030348 { > + compatible = "allwinner,sun20i-d1-analog-ldos"; > + reg = <0x2030348 0x4>; > + nvmem-cells = <&bg_trim>; > + nvmem-cell-names = "bg_trim"; > + > + reg_aldo: aldo { > + }; > + > + reg_hpldo: hpldo { > + }; > + }; > + }; Best regards, Krzysztof
On 15/08/2022 06:08, Samuel Holland wrote: > D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as > one HiFi 4 DSP. The SoC is based on a design that additionally contained > a pair of Cortex A7's. For that reason, some peripherals are duplicated. > > This devicetree includes all of the peripherals that already have a > documented binding. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Tested-by: Conor Dooley <conor.dooley@microchip.com> # Nezha D1 Thanks! > --- > > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/allwinner/Makefile | 1 + > arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++ > 3 files changed, 902 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/Makefile > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..f292e31bdb2c 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += allwinner > subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile > new file mode 100644 > index 000000000000..f66554cd5c45 > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/Makefile > @@ -0,0 +1 @@ > +# SPDX-License-Identifier: GPL-2.0 > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > new file mode 100644 > index 000000000000..d1429274f22e > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > @@ -0,0 +1,900 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> > + > +#include <dt-bindings/clock/sun6i-rtc.h> > +#include <dt-bindings/clock/sun8i-de2.h> > +#include <dt-bindings/clock/sun8i-tcon-top.h> > +#include <dt-bindings/clock/sun20i-d1-ccu.h> > +#include <dt-bindings/clock/sun20i-d1-r-ccu.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/reset/sun8i-de2.h> > +#include <dt-bindings/reset/sun20i-d1-ccu.h> > +#include <dt-bindings/reset/sun20i-d1-r-ccu.h> > +#include <dt-bindings/thermal/thermal.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <24000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + clocks = <&ccu CLK_RISCV>; > + clock-frequency = <24000000>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + #cooling-cells = <2>; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + de: display-engine { > + compatible = "allwinner,sun20i-d1-display-engine"; > + allwinner,pipelines = <&mixer0>, <&mixer1>; > + status = "disabled"; > + }; > + > + osc24M: osc24M-clk { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + dsp_wdt: watchdog@1700400 { > + compatible = "allwinner,sun20i-d1-wdt"; > + reg = <0x1700400 0x20>; > + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>, <&rtc CLK_OSC32K>; > + clock-names = "hosc", "losc"; > + status = "reserved"; > + }; > + > + pio: pinctrl@2000000 { > + compatible = "allwinner,sun20i-d1-pinctrl"; > + reg = <0x2000000 0x800>; > + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>, > + <87 IRQ_TYPE_LEVEL_HIGH>, > + <89 IRQ_TYPE_LEVEL_HIGH>, > + <91 IRQ_TYPE_LEVEL_HIGH>, > + <93 IRQ_TYPE_LEVEL_HIGH>, > + <95 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_APB0>, > + <&osc24M>, > + <&rtc CLK_OSC32K>; > + clock-names = "apb", "hosc", "losc"; > + gpio-controller; > + interrupt-controller; > + #gpio-cells = <3>; > + #interrupt-cells = <3>; > + > + /omit-if-no-ref/ > + i2c0_pb10_pins: i2c0-pb10-pins { > + pins = "PB10", "PB11"; > + function = "i2c0"; > + }; > + > + /omit-if-no-ref/ > + i2c2_pb0_pins: i2c2-pb0-pins { > + pins = "PB0", "PB1"; > + function = "i2c2"; > + }; > + > + /omit-if-no-ref/ > + lcd_rgb666_pins: lcd-rgb666-pins { > + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", > + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", > + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", > + "PD18", "PD19", "PD20", "PD21"; > + function = "lcd0"; > + }; > + > + /omit-if-no-ref/ > + mmc0_pins: mmc0-pins { > + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; > + function = "mmc0"; > + }; > + > + /omit-if-no-ref/ > + mmc1_pins: mmc1-pins { > + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; > + function = "mmc1"; > + }; > + > + /omit-if-no-ref/ > + mmc2_pins: mmc2-pins { > + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; > + function = "mmc2"; > + }; > + > + /omit-if-no-ref/ > + rgmii_pe_pins: rgmii-pe-pins { > + pins = "PE0", "PE1", "PE2", "PE3", "PE4", > + "PE5", "PE6", "PE7", "PE8", "PE9", > + "PE11", "PE12", "PE13", "PE14", "PE15"; > + function = "emac"; > + }; > + > + /omit-if-no-ref/ > + rmii_pe_pins: rmii-pe-pins { > + pins = "PE0", "PE1", "PE2", "PE3", "PE4", > + "PE5", "PE6", "PE7", "PE8", "PE9"; > + function = "emac"; > + }; > + > + /omit-if-no-ref/ > + uart0_pb8_pins: uart0-pb8-pins { > + pins = "PB8", "PB9"; > + function = "uart0"; > + }; > + > + /omit-if-no-ref/ > + uart1_pg6_pins: uart1-pg6-pins { > + pins = "PG6", "PG7"; > + function = "uart1"; > + }; > + > + /omit-if-no-ref/ > + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { > + pins = "PG8", "PG9"; > + function = "uart1"; > + }; > + }; > + > + ccu: clock-controller@2001000 { > + compatible = "allwinner,sun20i-d1-ccu"; > + reg = <0x2001000 0x1000>; > + clocks = <&osc24M>, > + <&rtc CLK_OSC32K>, > + <&rtc CLK_IOSC>; > + clock-names = "hosc", "losc", "iosc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + lradc: keys@2009800 { > + compatible = "allwinner,sun20i-d1-lradc", > + "allwinner,sun50i-r329-lradc"; > + reg = <0x2009800 0x400>; > + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_LRADC>; > + resets = <&ccu RST_BUS_LRADC>; > + status = "disabled"; > + }; > + > + codec: audio-codec@2030000 { > + compatible = "simple-mfd", "syscon"; > + reg = <0x2030000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + regulators@2030348 { > + compatible = "allwinner,sun20i-d1-analog-ldos"; > + reg = <0x2030348 0x4>; > + nvmem-cells = <&bg_trim>; > + nvmem-cell-names = "bg_trim"; > + > + reg_aldo: aldo { > + }; > + > + reg_hpldo: hpldo { > + }; > + }; > + }; > + > + i2s0: i2s@2032000 { > + compatible = "allwinner,sun20i-d1-i2s", > + "allwinner,sun50i-r329-i2s"; > + reg = <0x2032000 0x1000>; > + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2S0>, > + <&ccu CLK_I2S0>; > + clock-names = "apb", "mod"; > + resets = <&ccu RST_BUS_I2S0>; > + dmas = <&dma 3>, <&dma 3>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #sound-dai-cells = <0>; > + }; > + > + i2s1: i2s@2033000 { > + compatible = "allwinner,sun20i-d1-i2s", > + "allwinner,sun50i-r329-i2s"; > + reg = <0x2033000 0x1000>; > + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2S1>, > + <&ccu CLK_I2S1>; > + clock-names = "apb", "mod"; > + resets = <&ccu RST_BUS_I2S1>; > + dmas = <&dma 4>, <&dma 4>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #sound-dai-cells = <0>; > + }; > + > + i2s2: i2s@2034000 { > + compatible = "allwinner,sun20i-d1-i2s", > + "allwinner,sun50i-r329-i2s"; > + reg = <0x2034000 0x1000>; > + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2S2>, > + <&ccu CLK_I2S2>; > + clock-names = "apb", "mod"; > + resets = <&ccu RST_BUS_I2S2>; > + dmas = <&dma 5>, <&dma 5>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #sound-dai-cells = <0>; > + }; > + > + timer: timer@2050000 { > + compatible = "allwinner,sun20i-d1-timer", > + "allwinner,sun8i-a23-timer"; > + reg = <0x2050000 0xa0>; > + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>, > + <76 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>; > + }; > + > + wdt: watchdog@20500a0 { > + compatible = "allwinner,sun20i-d1-wdt-reset", > + "allwinner,sun20i-d1-wdt"; > + reg = <0x20500a0 0x20>; > + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>, <&rtc CLK_OSC32K>; > + clock-names = "hosc", "losc"; > + status = "reserved"; > + }; > + > + uart0: serial@2500000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2500000 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART0>; > + resets = <&ccu RST_BUS_UART0>; > + dmas = <&dma 14>, <&dma 14>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart1: serial@2500400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2500400 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART1>; > + resets = <&ccu RST_BUS_UART1>; > + dmas = <&dma 15>, <&dma 15>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart2: serial@2500800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2500800 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART2>; > + resets = <&ccu RST_BUS_UART2>; > + dmas = <&dma 16>, <&dma 16>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart3: serial@2500c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2500c00 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART3>; > + resets = <&ccu RST_BUS_UART3>; > + dmas = <&dma 17>, <&dma 17>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart4: serial@2501000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2501000 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART4>; > + resets = <&ccu RST_BUS_UART4>; > + dmas = <&dma 18>, <&dma 18>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart5: serial@2501400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x2501400 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_UART5>; > + resets = <&ccu RST_BUS_UART5>; > + dmas = <&dma 19>, <&dma 19>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + i2c0: i2c@2502000 { > + compatible = "allwinner,sun20i-d1-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x2502000 0x400>; > + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + dmas = <&dma 43>, <&dma 43>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c1: i2c@2502400 { > + compatible = "allwinner,sun20i-d1-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x2502400 0x400>; > + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + dmas = <&dma 44>, <&dma 44>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c2: i2c@2502800 { > + compatible = "allwinner,sun20i-d1-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x2502800 0x400>; > + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + dmas = <&dma 45>, <&dma 45>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c3: i2c@2502c00 { > + compatible = "allwinner,sun20i-d1-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x2502c00 0x400>; > + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C3>; > + resets = <&ccu RST_BUS_I2C3>; > + dmas = <&dma 46>, <&dma 46>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + syscon: syscon@3000000 { > + compatible = "allwinner,sun20i-d1-system-control"; > + reg = <0x3000000 0x1000>; > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + > + regulators@3000150 { > + compatible = "allwinner,sun20i-d1-system-ldos"; > + reg = <0x3000150 0x4>; > + > + reg_ldoa: ldoa { > + }; > + > + reg_ldob: ldob { > + }; > + }; > + }; > + > + dma: dma-controller@3002000 { > + compatible = "allwinner,sun20i-d1-dma"; > + reg = <0x3002000 0x1000>; > + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; > + clock-names = "bus", "mbus"; > + resets = <&ccu RST_BUS_DMA>; > + dma-channels = <16>; > + dma-requests = <48>; > + #dma-cells = <1>; > + }; > + > + sid: efuse@3006000 { > + compatible = "allwinner,sun20i-d1-sid"; > + reg = <0x3006000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + ths_calib: ths-calib@14 { > + reg = <0x14 0x4>; > + }; > + > + bg_trim: bg-trim@28 { > + reg = <0x28 0x4>; > + bits = <16 8>; > + }; > + }; > + > + mbus: dram-controller@3102000 { > + compatible = "allwinner,sun20i-d1-mbus"; > + reg = <0x3102000 0x1000>, > + <0x3103000 0x1000>; > + reg-names = "mbus", "dram"; > + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_MBUS>, > + <&ccu CLK_DRAM>, > + <&ccu CLK_BUS_DRAM>; > + clock-names = "mbus", "dram", "bus"; > + dma-ranges = <0 0x40000000 0x80000000>; > + #address-cells = <1>; > + #size-cells = <1>; > + #interconnect-cells = <1>; > + }; > + > + mmc0: mmc@4020000 { > + compatible = "allwinner,sun20i-d1-mmc"; > + reg = <0x4020000 0x1000>; > + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC0>; > + reset-names = "ahb"; > + cap-sd-highspeed; > + max-frequency = <150000000>; > + no-mmc; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc1: mmc@4021000 { > + compatible = "allwinner,sun20i-d1-mmc"; > + reg = <0x4021000 0x1000>; > + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC1>; > + reset-names = "ahb"; > + cap-sd-highspeed; > + max-frequency = <150000000>; > + no-mmc; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc2: mmc@4022000 { > + compatible = "allwinner,sun20i-d1-emmc", > + "allwinner,sun50i-a100-emmc"; > + reg = <0x4022000 0x1000>; > + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC2>; > + reset-names = "ahb"; > + cap-mmc-highspeed; > + max-frequency = <150000000>; > + mmc-ddr-1_8v; > + mmc-ddr-3_3v; > + no-sd; > + no-sdio; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + usb_otg: usb@4100000 { > + compatible = "allwinner,sun20i-d1-musb", > + "allwinner,sun8i-a33-musb"; > + reg = <0x4100000 0x400>; > + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mc"; > + clocks = <&ccu CLK_BUS_OTG>; > + resets = <&ccu RST_BUS_OTG>; > + extcon = <&usbphy 0>; > + phys = <&usbphy 0>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + usbphy: phy@4100400 { > + compatible = "allwinner,sun20i-d1-usb-phy"; > + reg = <0x4100400 0x100>, > + <0x4101800 0x100>, > + <0x4200800 0x100>; > + reg-names = "phy_ctrl", > + "pmu0", > + "pmu1"; > + clocks = <&osc24M>, > + <&osc24M>; > + clock-names = "usb0_phy", > + "usb1_phy"; > + resets = <&ccu RST_USB_PHY0>, > + <&ccu RST_USB_PHY1>; > + reset-names = "usb0_reset", > + "usb1_reset"; > + status = "disabled"; > + #phy-cells = <1>; > + }; > + > + ehci0: usb@4101000 { > + compatible = "allwinner,sun20i-d1-ehci", > + "generic-ehci"; > + reg = <0x4101000 0x100>; > + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_BUS_EHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets = <&ccu RST_BUS_OHCI0>, > + <&ccu RST_BUS_EHCI0>; > + phys = <&usbphy 0>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci0: usb@4101400 { > + compatible = "allwinner,sun20i-d1-ohci", > + "generic-ohci"; > + reg = <0x4101400 0x100>; > + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets = <&ccu RST_BUS_OHCI0>; > + phys = <&usbphy 0>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ehci1: usb@4200000 { > + compatible = "allwinner,sun20i-d1-ehci", > + "generic-ehci"; > + reg = <0x4200000 0x100>; > + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_BUS_EHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets = <&ccu RST_BUS_OHCI1>, > + <&ccu RST_BUS_EHCI1>; > + phys = <&usbphy 1>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci1: usb@4200400 { > + compatible = "allwinner,sun20i-d1-ohci", > + "generic-ohci"; > + reg = <0x4200400 0x100>; > + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets = <&ccu RST_BUS_OHCI1>; > + phys = <&usbphy 1>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + emac: ethernet@4500000 { > + compatible = "allwinner,sun20i-d1-emac", > + "allwinner,sun50i-a64-emac"; > + reg = <0x4500000 0x10000>; > + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq"; > + clocks = <&ccu CLK_BUS_EMAC>; > + clock-names = "stmmaceth"; > + resets = <&ccu RST_BUS_EMAC>; > + reset-names = "stmmaceth"; > + syscon = <&syscon>; > + status = "disabled"; > + > + mdio: mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + display_clocks: clock-controller@5000000 { > + compatible = "allwinner,sun20i-d1-de2-clk", > + "allwinner,sun50i-h5-de2-clk"; > + reg = <0x5000000 0x10000>; > + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_DE>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + mixer0: mixer@5100000 { > + compatible = "allwinner,sun20i-d1-de2-mixer-0"; > + reg = <0x5100000 0x100000>; > + clocks = <&display_clocks CLK_BUS_MIXER0>, > + <&display_clocks CLK_MIXER0>; > + clock-names = "bus", "mod"; > + resets = <&display_clocks RST_MIXER0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mixer0_out: port@1 { > + reg = <1>; > + > + mixer0_out_tcon_top_mixer0: endpoint { > + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; > + }; > + }; > + }; > + }; > + > + mixer1: mixer@5200000 { > + compatible = "allwinner,sun20i-d1-de2-mixer-1"; > + reg = <0x5200000 0x100000>; > + clocks = <&display_clocks CLK_BUS_MIXER1>, > + <&display_clocks CLK_MIXER1>; > + clock-names = "bus", "mod"; > + resets = <&display_clocks RST_MIXER1>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mixer1_out: port@1 { > + reg = <1>; > + > + mixer1_out_tcon_top_mixer1: endpoint { > + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; > + }; > + }; > + }; > + }; > + > + tcon_top: tcon-top@5460000 { > + compatible = "allwinner,sun20i-d1-tcon-top"; > + reg = <0x5460000 0x1000>; > + clocks = <&ccu CLK_BUS_DPSS_TOP>, > + <&ccu CLK_TCON_TV>, > + <&ccu CLK_TVE>, > + <&ccu CLK_MIPI_DSI>; > + clock-names = "bus", "tcon-tv0", "tve0", "dsi"; > + clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; > + resets = <&ccu RST_BUS_DPSS_TOP>; > + #clock-cells = <1>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer0_in: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer0_in_mixer0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&mixer0_out_tcon_top_mixer0>; > + }; > + }; > + > + tcon_top_mixer0_out: port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; > + }; > + > + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { > + reg = <2>; > + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; > + }; > + }; > + > + tcon_top_mixer1_in: port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer1_in_mixer1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&mixer1_out_tcon_top_mixer1>; > + }; > + }; > + > + tcon_top_mixer1_out: port@3 { > + reg = <3>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; > + }; > + > + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { > + reg = <2>; > + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; > + }; > + }; > + > + tcon_top_hdmi_in: port@4 { > + reg = <4>; > + > + tcon_top_hdmi_in_tcon_tv0: endpoint { > + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; > + }; > + }; > + > + tcon_top_hdmi_out: port@5 { > + reg = <5>; > + }; > + }; > + }; > + > + tcon_lcd0: lcd-controller@5461000 { > + compatible = "allwinner,sun20i-d1-tcon-lcd"; > + reg = <0x5461000 0x1000>; > + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_TCON_LCD0>, > + <&ccu CLK_TCON_LCD0>; > + clock-names = "ahb", "tcon-ch0"; > + clock-output-names = "tcon-pixel-clock"; > + resets = <&ccu RST_BUS_TCON_LCD0>, > + <&ccu RST_BUS_LVDS0>; > + reset-names = "lcd", "lvds"; > + #clock-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_lcd0_in: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; > + }; > + > + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; > + }; > + }; > + > + tcon_lcd0_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > + tcon_tv0: lcd-controller@5470000 { > + compatible = "allwinner,sun20i-d1-tcon-tv"; > + reg = <0x5470000 0x1000>; > + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_TCON_TV>, > + <&tcon_top CLK_TCON_TOP_TV0>; > + clock-names = "ahb", "tcon-ch1"; > + resets = <&ccu RST_BUS_TCON_TV>; > + reset-names = "lcd"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_tv0_in: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; > + }; > + > + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; > + }; > + }; > + > + tcon_tv0_out: port@1 { > + reg = <1>; > + > + tcon_tv0_out_tcon_top_hdmi: endpoint { > + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; > + }; > + }; > + }; > + }; > + > + riscv_wdt: watchdog@6011000 { > + compatible = "allwinner,sun20i-d1-wdt"; > + reg = <0x6011000 0x20>; > + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>, <&rtc CLK_OSC32K>; > + clock-names = "hosc", "losc"; > + }; > + > + r_ccu: clock-controller@7010000 { > + compatible = "allwinner,sun20i-d1-r-ccu"; > + reg = <0x7010000 0x400>; > + clocks = <&osc24M>, > + <&rtc CLK_OSC32K>, > + <&rtc CLK_IOSC>, > + <&ccu CLK_PLL_PERIPH0_DIV3>; > + clock-names = "hosc", "losc", "iosc", "pll-periph"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + rtc: rtc@7090000 { > + compatible = "allwinner,sun20i-d1-rtc", > + "allwinner,sun50i-r329-rtc"; > + reg = <0x7090000 0x400>; > + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&r_ccu CLK_BUS_R_RTC>, > + <&osc24M>, > + <&r_ccu CLK_R_AHB>; > + clock-names = "bus", "hosc", "ahb"; > + #clock-cells = <1>; > + }; > + > + plic: interrupt-controller@10000000 { > + compatible = "allwinner,sun20i-d1-plic", > + "thead,c900-plic"; > + reg = <0x10000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, > + <&cpu0_intc 9>; > + interrupt-controller; > + riscv,ndev = <176>; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + }; > + }; > +};
On 8/15/22 12:01 PM, Conor.Dooley@microchip.com wrote: > On 15/08/2022 14:11, Andre Przywara wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> On Mon, 15 Aug 2022 00:08:09 -0500 >> Samuel Holland <samuel@sholland.org> wrote: >> >> Hi, >> >> thanks for all the efforts in getting those SoC peripherals supported! >> >>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as >>> one HiFi 4 DSP. The SoC is based on a design that additionally contained >>> a pair of Cortex A7's. For that reason, some peripherals are duplicated. >> >> So because of this, the Allwinner R528 and T113 SoCs would share almost >> everything in this file. Would it be useful to already split this DT up? >> To have a base .dtsi, basically this file without /cpus and /soc/plic, >> then have a RISC-V specific file with just those, including the base? >> There is precedence for this across-arch(-directories) sharing with the >> Raspberry Pi and Allwinner H3/H5 SoCs. > > For those playing along at home, one example is the arm64 bananapi m2 > dts which looks like: >> /dts-v1/; >> #include "sun50i-h5.dtsi" >> #include "sun50i-h5-cpu-opp.dtsi" >> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi> >> >> / { >> model = "Banana Pi BPI-M2-Plus v1.2 H5"; >> compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5"; >> }; > > I think this is a pretty good idea, and putting in the modularity up > front seems logical to me, so when the arm one does eventually get > added it can be done by only touching a single arch. This is not feasible, due to the different #interrupt-cells. See https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ Even if we share some file across architectures, you still have to update files in both places to get the interrupts properties correct. I get the desire to deduplicate things, but we already deal with updating the same/similar nodes across several SoCs, so that is nothing new. I think it would be more confusing/complicated to have all of the interrupts properties overridden in a separate file. Regards, Samuel
On 20/08/2022 18:24, Samuel Holland wrote: > On 8/15/22 12:01 PM, Conor.Dooley@microchip.com wrote: >> On 15/08/2022 14:11, Andre Przywara wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> On Mon, 15 Aug 2022 00:08:09 -0500 >>> Samuel Holland <samuel@sholland.org> wrote: >>> >>> Hi, >>> >>> thanks for all the efforts in getting those SoC peripherals supported! >>> >>>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as >>>> one HiFi 4 DSP. The SoC is based on a design that additionally contained >>>> a pair of Cortex A7's. For that reason, some peripherals are duplicated. >>> >>> So because of this, the Allwinner R528 and T113 SoCs would share almost >>> everything in this file. Would it be useful to already split this DT up? >>> To have a base .dtsi, basically this file without /cpus and /soc/plic, >>> then have a RISC-V specific file with just those, including the base? >>> There is precedence for this across-arch(-directories) sharing with the >>> Raspberry Pi and Allwinner H3/H5 SoCs. >> >> For those playing along at home, one example is the arm64 bananapi m2 >> dts which looks like: >>> /dts-v1/; >>> #include "sun50i-h5.dtsi" >>> #include "sun50i-h5-cpu-opp.dtsi" >>> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi> >>> >>> / { >>> model = "Banana Pi BPI-M2-Plus v1.2 H5"; >>> compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5"; >>> }; >> >> I think this is a pretty good idea, and putting in the modularity up >> front seems logical to me, so when the arm one does eventually get >> added it can be done by only touching a single arch. > > This is not feasible, due to the different #interrupt-cells. See > https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > > Even if we share some file across architectures, you still have to update files > in both places to get the interrupts properties correct. > > I get the desire to deduplicate things, but we already deal with updating the > same/similar nodes across several SoCs, so that is nothing new. I think it would > be more confusing/complicated to have all of the interrupts properties > overridden in a separate file. Yeah, should maybe have circled back after that conversation, would have been nice but if the DTC can't do it nicely then w/e.
在 2022-08-20星期六的 17:29 +0000，Conor.Dooley@microchip.com写道： > On 20/08/2022 18:24, Samuel Holland wrote: > > On 8/15/22 12:01 PM, Conor.Dooley@microchip.com wrote: > > > On 15/08/2022 14:11, Andre Przywara wrote: > > > > EXTERNAL EMAIL: Do not click links or open attachments unless > > > > you know the content is safe > > > > > > > > On Mon, 15 Aug 2022 00:08:09 -0500 > > > > Samuel Holland <samuel@sholland.org> wrote: > > > > > > > > Hi, > > > > > > > > thanks for all the efforts in getting those SoC peripherals > > > > supported! > > > > > > > > > D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, > > > > > as well as > > > > > one HiFi 4 DSP. The SoC is based on a design that > > > > > additionally contained > > > > > a pair of Cortex A7's. For that reason, some peripherals are > > > > > duplicated. > > > > > > > > So because of this, the Allwinner R528 and T113 SoCs would > > > > share almost > > > > everything in this file. Would it be useful to already split > > > > this DT up? > > > > To have a base .dtsi, basically this file without /cpus and > > > > /soc/plic, > > > > then have a RISC-V specific file with just those, including the > > > > base? > > > > There is precedence for this across-arch(-directories) sharing > > > > with the > > > > Raspberry Pi and Allwinner H3/H5 SoCs. > > > > > > For those playing along at home, one example is the arm64 > > > bananapi m2 > > > dts which looks like: > > > > /dts-v1/; > > > > #include "sun50i-h5.dtsi" > > > > #include "sun50i-h5-cpu-opp.dtsi" > > > > #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi> > > > > > > > > / { > > > > model = "Banana Pi BPI-M2-Plus v1.2 H5"; > > > > compatible = "bananapi,bpi-m2-plus-v1.2", > > > > "allwinner,sun50i-h5"; > > > > }; > > > > > > I think this is a pretty good idea, and putting in the modularity > > > up > > > front seems logical to me, so when the arm one does eventually > > > get > > > added it can be done by only touching a single arch. > > > > This is not feasible, due to the different #interrupt-cells. See > > https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > > > > Even if we share some file across architectures, you still have to > > update files > > in both places to get the interrupts properties correct. > > > > I get the desire to deduplicate things, but we already deal with > > updating the > > same/similar nodes across several SoCs, so that is nothing new. I > > think it would > > be more confusing/complicated to have all of the interrupts > > properties > > overridden in a separate file. > > Yeah, should maybe have circled back after that conversation, would > have been > nice but if the DTC can't do it nicely then w/e. Well, maybe we can overuse the facility of C preprocessor? e.g. ``` // For ARM #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n // For RISC-V #define SOC_PERIPHERAL_IRQ(n) n ```
On 21/08/2022 07:45, Icenowy Zheng wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > 在 2022-08-20星期六的 17:29 +0000，Conor.Dooley@microchip.com写道： >> On 20/08/2022 18:24, Samuel Holland wrote: >>> On 8/15/22 12:01 PM, Conor.Dooley@microchip.com wrote: >>>> On 15/08/2022 14:11, Andre Przywara wrote: >>>>> EXTERNAL EMAIL: Do not click links or open attachments unless >>>>> you know the content is safe >>>>> >>>>> On Mon, 15 Aug 2022 00:08:09 -0500 >>>>> Samuel Holland <samuel@sholland.org> wrote: >>>>> >>>>> Hi, >>>>> >>>>> thanks for all the efforts in getting those SoC peripherals >>>>> supported! >>>>> >>>>>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, >>>>>> as well as >>>>>> one HiFi 4 DSP. The SoC is based on a design that >>>>>> additionally contained >>>>>> a pair of Cortex A7's. For that reason, some peripherals are >>>>>> duplicated. >>>>> >>>>> So because of this, the Allwinner R528 and T113 SoCs would >>>>> share almost >>>>> everything in this file. Would it be useful to already split >>>>> this DT up? >>>>> To have a base .dtsi, basically this file without /cpus and >>>>> /soc/plic, >>>>> then have a RISC-V specific file with just those, including the >>>>> base? >>>>> There is precedence for this across-arch(-directories) sharing >>>>> with the >>>>> Raspberry Pi and Allwinner H3/H5 SoCs. >>>> >>>> For those playing along at home, one example is the arm64 >>>> bananapi m2 >>>> dts which looks like: >>>>> /dts-v1/; >>>>> #include "sun50i-h5.dtsi" >>>>> #include "sun50i-h5-cpu-opp.dtsi" >>>>> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi> >>>>> >>>>> / { >>>>> model = "Banana Pi BPI-M2-Plus v1.2 H5"; >>>>> compatible = "bananapi,bpi-m2-plus-v1.2", >>>>> "allwinner,sun50i-h5"; >>>>> }; >>>> >>>> I think this is a pretty good idea, and putting in the modularity >>>> up >>>> front seems logical to me, so when the arm one does eventually >>>> get >>>> added it can be done by only touching a single arch. >>> >>> This is not feasible, due to the different #interrupt-cells. See >>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ >>> >>> Even if we share some file across architectures, you still have to >>> update files >>> in both places to get the interrupts properties correct. >>> >>> I get the desire to deduplicate things, but we already deal with >>> updating the >>> same/similar nodes across several SoCs, so that is nothing new. I >>> think it would >>> be more confusing/complicated to have all of the interrupts >>> properties >>> overridden in a separate file. >> >> Yeah, should maybe have circled back after that conversation, would >> have been >> nice but if the DTC can't do it nicely then w/e. > > Well, maybe we can overuse the facility of C preprocessor? > > e.g. > > ``` > // For ARM > #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n > // For RISC-V > #define SOC_PERIPHERAL_IRQ(n) n > ``` > Geert pointed out that this is not possible (at least on the Renesas stuff) because the GIC interrupt numbers are not the same as the PLIC's & the DTC is not able to handle the addition: https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ Thanks, Conor.
On Sat, 20 Aug 2022 12:24:55 -0500 Samuel Holland <samuel@sholland.org> wrote: Hi, > On 8/15/22 12:01 PM, Conor.Dooley@microchip.com wrote: > > On 15/08/2022 14:11, Andre Przywara wrote: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >> > >> On Mon, 15 Aug 2022 00:08:09 -0500 > >> Samuel Holland <samuel@sholland.org> wrote: > >> > >> Hi, > >> > >> thanks for all the efforts in getting those SoC peripherals supported! > >> > >>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as > >>> one HiFi 4 DSP. The SoC is based on a design that additionally contained > >>> a pair of Cortex A7's. For that reason, some peripherals are duplicated. > >> > >> So because of this, the Allwinner R528 and T113 SoCs would share almost > >> everything in this file. Would it be useful to already split this DT up? > >> To have a base .dtsi, basically this file without /cpus and /soc/plic, > >> then have a RISC-V specific file with just those, including the base? > >> There is precedence for this across-arch(-directories) sharing with the > >> Raspberry Pi and Allwinner H3/H5 SoCs. > > > > For those playing along at home, one example is the arm64 bananapi m2 > > dts which looks like: > >> /dts-v1/; > >> #include "sun50i-h5.dtsi" > >> #include "sun50i-h5-cpu-opp.dtsi" > >> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi> > >> > >> / { > >> model = "Banana Pi BPI-M2-Plus v1.2 H5"; > >> compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5"; > >> }; > > > > I think this is a pretty good idea, and putting in the modularity up > > front seems logical to me, so when the arm one does eventually get > > added it can be done by only touching a single arch. > > This is not feasible, due to the different #interrupt-cells. See > https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > > Even if we share some file across architectures, you still have to update files > in both places to get the interrupts properties correct. There are interrupt-maps for that: sun8i-r528.dtsi: soc { #interrupt-cells = <1>; interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, .... sun20i-d1.dtsi: soc { #interrupt-cells = <1>; interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>, <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>, then, in the shared .dtsi: uart0: serial@2500000 { compatible = "snps,dw-apb-uart"; ... interrupts = <18>; This is completely untested, but I have all the files spelt out there, and dtc seems happy for both architectures (outside of the kernel tree for now). > I get the desire to deduplicate things, but we already deal with updating the > same/similar nodes across several SoCs, so that is nothing new. I think it would > be more confusing/complicated to have all of the interrupts properties > overridden in a separate file. So is this the only thing that prevents sharing? The above paragraph sounds a bit you are not very fond of the idea to begin with? Cheers, Andre
Hi Jernej, On Tue, Aug 16, 2022 at 11:28 AM Jernej Škrabec <jernej.skrabec@gmail.com> wrote: > Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a): > > Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec: > > > Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski > napisal(a): > > > > On 15/08/2022 08:08, Samuel Holland wrote: > > > > > + > > > > > + de: display-engine { > > > > > + compatible = "allwinner,sun20i-d1-display-engine"; > > > > > + allwinner,pipelines = <&mixer0>, <&mixer1>; > > > > > + status = "disabled"; > > > > > + }; > > > > > + > > > > > + osc24M: osc24M-clk { > > > > > > > > lowercase > > > > > > > > > + compatible = "fixed-clock"; > > > > > + clock-frequency = <24000000>; > > > > > > > > This is a property of the board, not SoC. > > > > > > SoC needs 24 MHz oscillator for correct operation, so each and every board > > > has it. Having it here simplifies board DT files. > > > > I guess the oscillator is a separate component on each board, right? > > Correct. > > > And DT obvious is meant to describe the hardware - independently from > > implementation-specific choices. > > There is no choice in this case. 24 MHz crystal has to be present. > > FWIW, including crystal node in SoC specific DTSI is already common pattern in > Allwinner ARM SoC DTSI files. I could also be a programmable clock generator on the board, programmed to generate a 24 MHz clock on one of its outputs? Again, on the board. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Conor, Andre, On Sun, Aug 21, 2022 at 12:07 PM <Conor.Dooley@microchip.com> wrote: > On 21/08/2022 07:45, Icenowy Zheng wrote: > > 在 2022-08-20星期六的 17:29 +0000，Conor.Dooley@microchip.com写道： > >> On 20/08/2022 18:24, Samuel Holland wrote: > >>> On 8/15/22 12:01 PM, Conor.Dooley@microchip.com wrote: > >>>> On 15/08/2022 14:11, Andre Przywara wrote: > >>>>> EXTERNAL EMAIL: Do not click links or open attachments unless > >>>>> you know the content is safe > >>>>> > >>>>> On Mon, 15 Aug 2022 00:08:09 -0500 > >>>>> Samuel Holland <samuel@sholland.org> wrote: > >>>>> > >>>>> Hi, > >>>>> > >>>>> thanks for all the efforts in getting those SoC peripherals > >>>>> supported! > >>>>> > >>>>>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, > >>>>>> as well as > >>>>>> one HiFi 4 DSP. The SoC is based on a design that > >>>>>> additionally contained > >>>>>> a pair of Cortex A7's. For that reason, some peripherals are > >>>>>> duplicated. > >>>>> > >>>>> So because of this, the Allwinner R528 and T113 SoCs would > >>>>> share almost > >>>>> everything in this file. Would it be useful to already split > >>>>> this DT up? > >>>>> To have a base .dtsi, basically this file without /cpus and > >>>>> /soc/plic, > >>>>> then have a RISC-V specific file with just those, including the > >>>>> base? > >>>>> There is precedence for this across-arch(-directories) sharing > >>>>> with the > >>>>> Raspberry Pi and Allwinner H3/H5 SoCs. > >>>> > >>>> For those playing along at home, one example is the arm64 > >>>> bananapi m2 > >>>> dts which looks like: > >>>>> /dts-v1/; > >>>>> #include "sun50i-h5.dtsi" > >>>>> #include "sun50i-h5-cpu-opp.dtsi" > >>>>> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi> > >>>>> > >>>>> / { > >>>>> model = "Banana Pi BPI-M2-Plus v1.2 H5"; > >>>>> compatible = "bananapi,bpi-m2-plus-v1.2", > >>>>> "allwinner,sun50i-h5"; > >>>>> }; > >>>> > >>>> I think this is a pretty good idea, and putting in the modularity > >>>> up > >>>> front seems logical to me, so when the arm one does eventually > >>>> get > >>>> added it can be done by only touching a single arch. > >>> > >>> This is not feasible, due to the different #interrupt-cells. See > >>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > >>> > >>> Even if we share some file across architectures, you still have to > >>> update files > >>> in both places to get the interrupts properties correct. > >>> > >>> I get the desire to deduplicate things, but we already deal with > >>> updating the > >>> same/similar nodes across several SoCs, so that is nothing new. I > >>> think it would > >>> be more confusing/complicated to have all of the interrupts > >>> properties > >>> overridden in a separate file. > >> > >> Yeah, should maybe have circled back after that conversation, would > >> have been > >> nice but if the DTC can't do it nicely then w/e. > > > > Well, maybe we can overuse the facility of C preprocessor? > > > > e.g. > > > > ``` > > // For ARM > > #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n > > // For RISC-V > > #define SOC_PERIPHERAL_IRQ(n) n > > ``` > > > > Geert pointed out that this is not possible (at least on the Renesas > stuff) because the GIC interrupt numbers are not the same as the > PLIC's & the DTC is not able to handle the addition: > https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ Without the ability to do additions in DTC, we could e.g. list both interrupts in the macro, like: // For ARM #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na // For RISC-V #define SOC_PERIPHERAL_IRQ(na, nr) nr On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <andre.przywara@arm.com> wrote: > There are interrupt-maps for that: > sun8i-r528.dtsi: > soc { > #interrupt-cells = <1>; > interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > .... > > sun20i-d1.dtsi: > soc { > #interrupt-cells = <1>; > interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>, > <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>, > > then, in the shared .dtsi: > uart0: serial@2500000 { > compatible = "snps,dw-apb-uart"; > ... > interrupts = <18>; Nice! But it's gonna be a very large interrupt-map. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hey Geert, On 22/08/2022 12:46, Geert Uytterhoeven wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Hi Conor, Andre, > > On Sun, Aug 21, 2022 at 12:07 PM <Conor.Dooley@microchip.com> wrote: >> On 21/08/2022 07:45, Icenowy Zheng wrote: >>> 在 2022-08-20星期六的 17:29 +0000，Conor.Dooley@microchip.com写道： >>>> On 20/08/2022 18:24, Samuel Holland wrote: >>>>> This is not feasible, due to the different #interrupt-cells. See >>>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ >>>>> >>>>> Even if we share some file across architectures, you still have to >>>>> update files >>>>> in both places to get the interrupts properties correct. >>>>> >>>>> I get the desire to deduplicate things, but we already deal with >>>>> updating the >>>>> same/similar nodes across several SoCs, so that is nothing new. I >>>>> think it would >>>>> be more confusing/complicated to have all of the interrupts >>>>> properties >>>>> overridden in a separate file. >>>> >>>> Yeah, should maybe have circled back after that conversation, would >>>> have been >>>> nice but if the DTC can't do it nicely then w/e. >>> >>> Well, maybe we can overuse the facility of C preprocessor? >>> >>> e.g. >>> >>> ``` >>> // For ARM >>> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n >>> // For RISC-V >>> #define SOC_PERIPHERAL_IRQ(n) n >>> ``` >>> >> >> Geert pointed out that this is not possible (at least on the Renesas >> stuff) because the GIC interrupt numbers are not the same as the >> PLIC's & the DTC is not able to handle the addition: >> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > > Without the ability to do additions in DTC, we could e.g. list both > interrupts in the macro, like: > > // For ARM > #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na > // For RISC-V > #define SOC_PERIPHERAL_IRQ(na, nr) nr Do you think this is worth doing? Or are you just providing an example of what could be done? Where would you envisage putting these macros? I forget the order of the CPP operations that are done, can they be put in the dts? > > On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <andre.przywara@arm.com> wrote: >> There are interrupt-maps for that: >> sun8i-r528.dtsi: >> soc { >> #interrupt-cells = <1>; >> interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, >> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, >> .... >> >> sun20i-d1.dtsi: >> soc { >> #interrupt-cells = <1>; >> interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>, >> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>, >> >> then, in the shared .dtsi: >> uart0: serial@2500000 { >> compatible = "snps,dw-apb-uart"; >> ... >> interrupts = <18>; > > Nice! But it's gonna be a very large interrupt-map. I quite like the idea of not duplicating files across the archs if it can be helped, but not at the expense of making them hard to understand & I feel like unfortunately the large interrupt map is in that territory. Thanks, Conor.
On Mon, 22 Aug 2022 12:13:42 +0000 <Conor.Dooley@microchip.com> wrote: Hi, > On 22/08/2022 12:46, Geert Uytterhoeven wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Hi Conor, Andre, > > > > On Sun, Aug 21, 2022 at 12:07 PM <Conor.Dooley@microchip.com> wrote: > >> On 21/08/2022 07:45, Icenowy Zheng wrote: > >>> 在 2022-08-20星期六的 17:29 +0000，Conor.Dooley@microchip.com写道： > >>>> On 20/08/2022 18:24, Samuel Holland wrote: > > >>>>> This is not feasible, due to the different #interrupt-cells. See > >>>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > >>>>> > >>>>> Even if we share some file across architectures, you still have to > >>>>> update files > >>>>> in both places to get the interrupts properties correct. > >>>>> > >>>>> I get the desire to deduplicate things, but we already deal with > >>>>> updating the > >>>>> same/similar nodes across several SoCs, so that is nothing new. I > >>>>> think it would > >>>>> be more confusing/complicated to have all of the interrupts > >>>>> properties > >>>>> overridden in a separate file. > >>>> > >>>> Yeah, should maybe have circled back after that conversation, would > >>>> have been > >>>> nice but if the DTC can't do it nicely then w/e. > >>> > >>> Well, maybe we can overuse the facility of C preprocessor? > >>> > >>> e.g. > >>> > >>> ``` > >>> // For ARM > >>> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n > >>> // For RISC-V > >>> #define SOC_PERIPHERAL_IRQ(n) n > >>> ``` > >>> > >> > >> Geert pointed out that this is not possible (at least on the Renesas > >> stuff) because the GIC interrupt numbers are not the same as the > >> PLIC's & the DTC is not able to handle the addition: > >> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > > > > Without the ability to do additions in DTC, we could e.g. list both > > interrupts in the macro, like: > > > > // For ARM > > #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na > > // For RISC-V > > #define SOC_PERIPHERAL_IRQ(na, nr) nr > > Do you think this is worth doing? Or are you just providing an > example of what could be done? > > Where would you envisage putting these macros? I forget the order > of the CPP operations that are done, can they be put in the dts? > > > > > On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <andre.przywara@arm.com> wrote: > >> There are interrupt-maps for that: > >> sun8i-r528.dtsi: > >> soc { > >> #interrupt-cells = <1>; > >> interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > >> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > >> .... > >> > >> sun20i-d1.dtsi: > >> soc { > >> #interrupt-cells = <1>; > >> interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>, > >> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>, > >> > >> then, in the shared .dtsi: > >> uart0: serial@2500000 { > >> compatible = "snps,dw-apb-uart"; > >> ... > >> interrupts = <18>; > > > > Nice! But it's gonna be a very large interrupt-map. > > I quite like the idea of not duplicating files across the archs > if it can be helped, but not at the expense of making them hard to > understand & I feel like unfortunately the large interrupt map is > in that territory. Well, I don't know about the Renesas case, but as far as we know the Allwinner D1 and R528 are using the exact same die, just fused differently. So expressing this in a common .dtsi sounds very desirable, especially since a devicetree is an architecture agnostic data structure. And while it's true that a DT interrupt-map is not for the faint of heart, I think even the casual reader gets the idea quickly by looking at it, possibly guided by a comment. And it doesn't need to be very large. grep counted 32 genuine interrupts in the current .dtsi file, so I just put those ones needed in. If we need more IRQs later (quite likely), they are easily added, using copy&paste. Cheers, Andre
Hi Conor, On Mon, Aug 22, 2022 at 2:13 PM <Conor.Dooley@microchip.com> wrote: > On 22/08/2022 12:46, Geert Uytterhoeven wrote: > > On Sun, Aug 21, 2022 at 12:07 PM <Conor.Dooley@microchip.com> wrote: > >> On 21/08/2022 07:45, Icenowy Zheng wrote: > >>> 在 2022-08-20星期六的 17:29 +0000，Conor.Dooley@microchip.com写道： > >>>> On 20/08/2022 18:24, Samuel Holland wrote: > > >>>>> This is not feasible, due to the different #interrupt-cells. See > >>>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > >>>>> > >>>>> Even if we share some file across architectures, you still have to > >>>>> update files > >>>>> in both places to get the interrupts properties correct. > >>>>> > >>>>> I get the desire to deduplicate things, but we already deal with > >>>>> updating the > >>>>> same/similar nodes across several SoCs, so that is nothing new. I > >>>>> think it would > >>>>> be more confusing/complicated to have all of the interrupts > >>>>> properties > >>>>> overridden in a separate file. > >>>> > >>>> Yeah, should maybe have circled back after that conversation, would > >>>> have been > >>>> nice but if the DTC can't do it nicely then w/e. > >>> > >>> Well, maybe we can overuse the facility of C preprocessor? > >>> > >>> e.g. > >>> > >>> ``` > >>> // For ARM > >>> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n > >>> // For RISC-V > >>> #define SOC_PERIPHERAL_IRQ(n) n > >>> ``` > >>> > >> > >> Geert pointed out that this is not possible (at least on the Renesas > >> stuff) because the GIC interrupt numbers are not the same as the > >> PLIC's & the DTC is not able to handle the addition: > >> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > > > > Without the ability to do additions in DTC, we could e.g. list both > > interrupts in the macro, like: > > > > // For ARM > > #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na > > // For RISC-V > > #define SOC_PERIPHERAL_IRQ(na, nr) nr > > Do you think this is worth doing? Or are you just providing an > example of what could be done? Just some brainstorming... > Where would you envisage putting these macros? I forget the order > of the CPP operations that are done, can they be put in the dts? The SOC_PERIPHERAL_IRQ() macro should be defined in the ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file. > > On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <andre.przywara@arm.com> wrote: > >> There are interrupt-maps for that: > >> sun8i-r528.dtsi: > >> soc { > >> #interrupt-cells = <1>; > >> interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > >> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > >> .... > >> > >> sun20i-d1.dtsi: > >> soc { > >> #interrupt-cells = <1>; > >> interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>, > >> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>, > >> > >> then, in the shared .dtsi: > >> uart0: serial@2500000 { > >> compatible = "snps,dw-apb-uart"; > >> ... > >> interrupts = <18>; > > > > Nice! But it's gonna be a very large interrupt-map. > > I quite like the idea of not duplicating files across the archs > if it can be helped, but not at the expense of making them hard to > understand & I feel like unfortunately the large interrupt map is > in that territory. I feel the same. Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr) is a risk for making mistakes. So personally, I'm in favor of teaching dtc arithmetic, so we can handle the offset in SOC_PERIPHERAL_IRQ(). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 22/08/2022 13:31, Geert Uytterhoeven wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >> Do you think this is worth doing? Or are you just providing an >> example of what could be done? > > Just some brainstorming... > >> Where would you envisage putting these macros? I forget the order >> of the CPP operations that are done, can they be put in the dts? > > The SOC_PERIPHERAL_IRQ() macro should be defined in the > ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file. Right, one level up but ~the same result. >>> Nice! But it's gonna be a very large interrupt-map. >> >> I quite like the idea of not duplicating files across the archs >> if it can be helped, but not at the expense of making them hard to >> understand & I feel like unfortunately the large interrupt map is >> in that territory. > > I feel the same. > Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr) > is a risk for making mistakes. > > So personally, I'm in favor of teaching dtc arithmetic, so we can > handle the offset in SOC_PERIPHERAL_IRQ(). Yup, in the same boat here. mayb I'll get bored enough to bite..
On 22 Aug 2022, at 14:56, conor.dooley@microchip.com wrote: > > On 22/08/2022 13:31, Geert Uytterhoeven wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> > > >>> Do you think this is worth doing? Or are you just providing an >>> example of what could be done? >> >> Just some brainstorming... >> >>> Where would you envisage putting these macros? I forget the order >>> of the CPP operations that are done, can they be put in the dts? >> >> The SOC_PERIPHERAL_IRQ() macro should be defined in the >> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file. > > Right, one level up but ~the same result. > > >>>> Nice! But it's gonna be a very large interrupt-map. >>> >>> I quite like the idea of not duplicating files across the archs >>> if it can be helped, but not at the expense of making them hard to >>> understand & I feel like unfortunately the large interrupt map is >>> in that territory. >> >> I feel the same. >> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr) >> is a risk for making mistakes. >> >> So personally, I'm in favor of teaching dtc arithmetic, so we can >> handle the offset in SOC_PERIPHERAL_IRQ(). > > Yup, in the same boat here. mayb I'll get bored enough to bite.. Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a BSD-licensed implementation[1] and so adding new features like this to GPL dtc that actually get used would require us to reimplement it too. I don’t know how much effort it would be but please keep this in mind. Jess [1] https://github.com/davidchisnall/dtc
On 8/22/22 10:29 AM, Jessica Clarke wrote: > On 22 Aug 2022, at 14:56, conor.dooley@microchip.com wrote: >> >> On 22/08/2022 13:31, Geert Uytterhoeven wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >> >> >>>> Do you think this is worth doing? Or are you just providing an >>>> example of what could be done? >>> >>> Just some brainstorming... >>> >>>> Where would you envisage putting these macros? I forget the order >>>> of the CPP operations that are done, can they be put in the dts? >>> >>> The SOC_PERIPHERAL_IRQ() macro should be defined in the >>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file. >> >> Right, one level up but ~the same result. >> >> >>>>> Nice! But it's gonna be a very large interrupt-map. >>>> >>>> I quite like the idea of not duplicating files across the archs >>>> if it can be helped, but not at the expense of making them hard to >>>> understand & I feel like unfortunately the large interrupt map is >>>> in that territory. >>> >>> I feel the same. >>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr) >>> is a risk for making mistakes. >>> >>> So personally, I'm in favor of teaching dtc arithmetic, so we can >>> handle the offset in SOC_PERIPHERAL_IRQ(). >> >> Yup, in the same boat here. mayb I'll get bored enough to bite.. > > Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a > BSD-licensed implementation[1] and so adding new features like this to > GPL dtc that actually get used would require us to reimplement it too. > I don’t know how much effort it would be but please keep this in mind. I plan to go with the "SOC_PERIPHERAL_IRQ(na, nr)" implementation for v2. I like that it only affects the DT source, and does not leak into the DTB. We still have the freedom to switch to using arithmetic later when all of the tools support it. My other concern is that the big interrupt-map property would make DT overlays even more painful to deal with. I don't think overlays can append to a property, only replace it. Regards, Samuel
Hi Samuel, On Fri, Sep 9, 2022 at 5:42 AM Samuel Holland <samuel@sholland.org> wrote: > On 8/22/22 10:29 AM, Jessica Clarke wrote: > > On 22 Aug 2022, at 14:56, conor.dooley@microchip.com wrote: > >> On 22/08/2022 13:31, Geert Uytterhoeven wrote: > >>>> Do you think this is worth doing? Or are you just providing an > >>>> example of what could be done? > >>> > >>> Just some brainstorming... > >>> > >>>> Where would you envisage putting these macros? I forget the order > >>>> of the CPP operations that are done, can they be put in the dts? > >>> > >>> The SOC_PERIPHERAL_IRQ() macro should be defined in the > >>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file. > >> > >> Right, one level up but ~the same result. > >> > >>>>> Nice! But it's gonna be a very large interrupt-map. > >>>> > >>>> I quite like the idea of not duplicating files across the archs > >>>> if it can be helped, but not at the expense of making them hard to > >>>> understand & I feel like unfortunately the large interrupt map is > >>>> in that territory. > >>> > >>> I feel the same. > >>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr) > >>> is a risk for making mistakes. > >>> > >>> So personally, I'm in favor of teaching dtc arithmetic, so we can > >>> handle the offset in SOC_PERIPHERAL_IRQ(). > >> > >> Yup, in the same boat here. mayb I'll get bored enough to bite.. > > > > Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a > > BSD-licensed implementation[1] and so adding new features like this to > > GPL dtc that actually get used would require us to reimplement it too. > > I don’t know how much effort it would be but please keep this in mind. > > I plan to go with the "SOC_PERIPHERAL_IRQ(na, nr)" implementation for v2. I like > that it only affects the DT source, and does not leak into the DTB. We still > have the freedom to switch to using arithmetic later when all of the tools > support it. May I suggest an alternative solution, which would be more generic, and can be extended to other/more CPU cores easily: Specify both interrupts in the .dtsi, but wrapped inside e.g. ARM() resp. RISCV() macros: ARM(interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;) RISCV(interrupts = <412 IRQ_TYPE_LEVEL_HIGH>;) The same construct can be used for e.g. interrupt-parent. The ARM .dts would define: #define ARM(x...) x #define RISCV(x....) before including the .dtsi. The RISC-V DTS would define instead: #define ARM(x...) #define RISCV(x...) x Cfr. the AR_CLASS(), M_CLASS(), ARM(), and THUMB() macros in arch/arm/include/asm/unified.h. Note that this is not exactly a new issue. It's fairly common for SoCs to have separate application and real-time cores, and on-SoC devices may be wired to multiple interrupt controllers serving the AP resp. RT cores. If both core sets are ARM, both interrupt controllers may be GIC, and the problem may be less severe and just need a different #interrupt-parent. But in case of ARM vs. RISC-V, or different wirings from devices to interrupt controllers, you do need completely different interrupts properties. > My other concern is that the big interrupt-map property would make DT overlays > even more painful to deal with. I don't think overlays can append to a property, > only replace it. Indeed, overlays can only add/replace/delete properties. Same for plain DTS files, BTW. But I agree having /append-property/ would be useful in general. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Fri, Sep 9, 2022 at 9:10 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Fri, Sep 9, 2022 at 5:42 AM Samuel Holland <samuel@sholland.org> wrote: > > On 8/22/22 10:29 AM, Jessica Clarke wrote: > > > On 22 Aug 2022, at 14:56, conor.dooley@microchip.com wrote: > > >> On 22/08/2022 13:31, Geert Uytterhoeven wrote: > > >>>> Do you think this is worth doing? Or are you just providing an > > >>>> example of what could be done? > > >>> > > >>> Just some brainstorming... > > >>> > > >>>> Where would you envisage putting these macros? I forget the order > > >>>> of the CPP operations that are done, can they be put in the dts? > > >>> > > >>> The SOC_PERIPHERAL_IRQ() macro should be defined in the > > >>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file. > > >> > > >> Right, one level up but ~the same result. > > >> > > >>>>> Nice! But it's gonna be a very large interrupt-map. > > >>>> > > >>>> I quite like the idea of not duplicating files across the archs > > >>>> if it can be helped, but not at the expense of making them hard to > > >>>> understand & I feel like unfortunately the large interrupt map is > > >>>> in that territory. > > >>> > > >>> I feel the same. > > >>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr) > > >>> is a risk for making mistakes. > > >>> > > >>> So personally, I'm in favor of teaching dtc arithmetic, so we can > > >>> handle the offset in SOC_PERIPHERAL_IRQ(). > > >> > > >> Yup, in the same boat here. mayb I'll get bored enough to bite.. > > > > > > Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a > > > BSD-licensed implementation[1] and so adding new features like this to > > > GPL dtc that actually get used would require us to reimplement it too. > > > I don’t know how much effort it would be but please keep this in mind. > > > > I plan to go with the "SOC_PERIPHERAL_IRQ(na, nr)" implementation for v2. I like > > that it only affects the DT source, and does not leak into the DTB. We still > > have the freedom to switch to using arithmetic later when all of the tools > > support it. > > May I suggest an alternative solution, which would be more generic, > and can be extended to other/more CPU cores easily: > > Specify both interrupts in the .dtsi, but wrapped inside e.g. ARM() > resp. RISCV() macros: > > ARM(interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;) > RISCV(interrupts = <412 IRQ_TYPE_LEVEL_HIGH>;) > > The same construct can be used for e.g. interrupt-parent. > The ARM .dts would define: > > #define ARM(x...) x > #define RISCV(x....) > > before including the .dtsi. > The RISC-V DTS would define instead: > > #define ARM(x...) > #define RISCV(x...) x > > Cfr. the AR_CLASS(), M_CLASS(), ARM(), and THUMB() macros in > arch/arm/include/asm/unified.h. I brought it up with the DT people in a separate thread[1]. Please continue the discussion there. Thanks! [1] https://lore.kernel.org/r/CAMuHMdUPm36RsxHdVwspR3NCAR3C507AyB6R65W42N2gXWq0ag@mail.gmail.com Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..f292e31bdb2c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += allwinner subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile new file mode 100644 index 000000000000..f66554cd5c45 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0 diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi new file mode 100644 index 000000000000..d1429274f22e --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi @@ -0,0 +1,900 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> + +#include <dt-bindings/clock/sun6i-rtc.h> +#include <dt-bindings/clock/sun8i-de2.h> +#include <dt-bindings/clock/sun8i-tcon-top.h> +#include <dt-bindings/clock/sun20i-d1-ccu.h> +#include <dt-bindings/clock/sun20i-d1-r-ccu.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/reset/sun20i-d1-ccu.h> +#include <dt-bindings/reset/sun20i-d1-r-ccu.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + timebase-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_RISCV>; + clock-frequency = <24000000>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + #cooling-cells = <2>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + de: display-engine { + compatible = "allwinner,sun20i-d1-display-engine"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + + osc24M: osc24M-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic>; + dma-noncoherent; + #address-cells = <1>; + #size-cells = <1>; + + dsp_wdt: watchdog@1700400 { + compatible = "allwinner,sun20i-d1-wdt"; + reg = <0x1700400 0x20>; + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + status = "reserved"; + }; + + pio: pinctrl@2000000 { + compatible = "allwinner,sun20i-d1-pinctrl"; + reg = <0x2000000 0x800>; + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>, + <87 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <91 IRQ_TYPE_LEVEL_HIGH>, + <93 IRQ_TYPE_LEVEL_HIGH>, + <95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB0>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #gpio-cells = <3>; + #interrupt-cells = <3>; + + /omit-if-no-ref/ + i2c0_pb10_pins: i2c0-pb10-pins { + pins = "PB10", "PB11"; + function = "i2c0"; + }; + + /omit-if-no-ref/ + i2c2_pb0_pins: i2c2-pb0-pins { + pins = "PB0", "PB1"; + function = "i2c2"; + }; + + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", + "PD18", "PD19", "PD20", "PD21"; + function = "lcd0"; + }; + + /omit-if-no-ref/ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; + function = "mmc1"; + }; + + /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function = "mmc2"; + }; + + /omit-if-no-ref/ + rgmii_pe_pins: rgmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE11", "PE12", "PE13", "PE14", "PE15"; + function = "emac"; + }; + + /omit-if-no-ref/ + rmii_pe_pins: rmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9"; + function = "emac"; + }; + + /omit-if-no-ref/ + uart0_pb8_pins: uart0-pb8-pins { + pins = "PB8", "PB9"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart1_pg6_pins: uart1-pg6-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; + }; + + ccu: clock-controller@2001000 { + compatible = "allwinner,sun20i-d1-ccu"; + reg = <0x2001000 0x1000>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + lradc: keys@2009800 { + compatible = "allwinner,sun20i-d1-lradc", + "allwinner,sun50i-r329-lradc"; + reg = <0x2009800 0x400>; + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_LRADC>; + resets = <&ccu RST_BUS_LRADC>; + status = "disabled"; + }; + + codec: audio-codec@2030000 { + compatible = "simple-mfd", "syscon"; + reg = <0x2030000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + regulators@2030348 { + compatible = "allwinner,sun20i-d1-analog-ldos"; + reg = <0x2030348 0x4>; + nvmem-cells = <&bg_trim>; + nvmem-cell-names = "bg_trim"; + + reg_aldo: aldo { + }; + + reg_hpldo: hpldo { + }; + }; + }; + + i2s0: i2s@2032000 { + compatible = "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x2032000 0x1000>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S0>, + <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S0>; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + status = "disabled"; + #sound-dai-cells = <0>; + }; + + i2s1: i2s@2033000 { + compatible = "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x2033000 0x1000>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S1>, + <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S1>; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + status = "disabled"; + #sound-dai-cells = <0>; + }; + + i2s2: i2s@2034000 { + compatible = "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x2034000 0x1000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S2>, + <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S2>; + dmas = <&dma 5>, <&dma 5>; + dma-names = "rx", "tx"; + status = "disabled"; + #sound-dai-cells = <0>; + }; + + timer: timer@2050000 { + compatible = "allwinner,sun20i-d1-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x2050000 0xa0>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>, + <76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + wdt: watchdog@20500a0 { + compatible = "allwinner,sun20i-d1-wdt-reset", + "allwinner,sun20i-d1-wdt"; + reg = <0x20500a0 0x20>; + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + status = "reserved"; + }; + + uart0: serial@2500000 { + compatible = "snps,dw-apb-uart"; + reg = <0x2500000 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@2500400 { + compatible = "snps,dw-apb-uart"; + reg = <0x2500400 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@2500800 { + compatible = "snps,dw-apb-uart"; + reg = <0x2500800 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@2500c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x2500c00 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@2501000 { + compatible = "snps,dw-apb-uart"; + reg = <0x2501000 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + dmas = <&dma 18>, <&dma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@2501400 { + compatible = "snps,dw-apb-uart"; + reg = <0x2501400 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + dmas = <&dma 19>, <&dma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c0: i2c@2502000 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502000 0x400>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@2502400 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502400 0x400>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@2502800 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502800 0x400>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@2502c00 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502c00 0x400>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + dmas = <&dma 46>, <&dma 46>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + syscon: syscon@3000000 { + compatible = "allwinner,sun20i-d1-system-control"; + reg = <0x3000000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + regulators@3000150 { + compatible = "allwinner,sun20i-d1-system-ldos"; + reg = <0x3000150 0x4>; + + reg_ldoa: ldoa { + }; + + reg_ldob: ldob { + }; + }; + }; + + dma: dma-controller@3002000 { + compatible = "allwinner,sun20i-d1-dma"; + reg = <0x3002000 0x1000>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + resets = <&ccu RST_BUS_DMA>; + dma-channels = <16>; + dma-requests = <48>; + #dma-cells = <1>; + }; + + sid: efuse@3006000 { + compatible = "allwinner,sun20i-d1-sid"; + reg = <0x3006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calib: ths-calib@14 { + reg = <0x14 0x4>; + }; + + bg_trim: bg-trim@28 { + reg = <0x28 0x4>; + bits = <16 8>; + }; + }; + + mbus: dram-controller@3102000 { + compatible = "allwinner,sun20i-d1-mbus"; + reg = <0x3102000 0x1000>, + <0x3103000 0x1000>; + reg-names = "mbus", "dram"; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + dma-ranges = <0 0x40000000 0x80000000>; + #address-cells = <1>; + #size-cells = <1>; + #interconnect-cells = <1>; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun20i-d1-mmc"; + reg = <0x4020000 0x1000>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + cap-sd-highspeed; + max-frequency = <150000000>; + no-mmc; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun20i-d1-mmc"; + reg = <0x4021000 0x1000>; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + cap-sd-highspeed; + max-frequency = <150000000>; + no-mmc; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun20i-d1-emmc", + "allwinner,sun50i-a100-emmc"; + reg = <0x4022000 0x1000>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + no-sd; + no-sdio; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@4100000 { + compatible = "allwinner,sun20i-d1-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x4100000 0x400>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + extcon = <&usbphy 0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: phy@4100400 { + compatible = "allwinner,sun20i-d1-usb-phy"; + reg = <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1"; + clocks = <&osc24M>, + <&osc24M>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@4101000 { + compatible = "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg = <0x4101000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@4101400 { + compatible = "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg = <0x4101400 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@4200000 { + compatible = "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg = <0x4200000 0x100>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@4200400 { + compatible = "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg = <0x4200400 0x100>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + emac: ethernet@4500000 { + compatible = "allwinner,sun20i-d1-emac", + "allwinner,sun50i-a64-emac"; + reg = <0x4500000 0x10000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + syscon = <&syscon>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + display_clocks: clock-controller@5000000 { + compatible = "allwinner,sun20i-d1-de2-clk", + "allwinner,sun50i-h5-de2-clk"; + reg = <0x5000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@5100000 { + compatible = "allwinner,sun20i-d1-de2-mixer-0"; + reg = <0x5100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@5200000 { + compatible = "allwinner,sun20i-d1-de2-mixer-1"; + reg = <0x5200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", "mod"; + resets = <&display_clocks RST_MIXER1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + + mixer1_out_tcon_top_mixer1: endpoint { + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + + tcon_top: tcon-top@5460000 { + compatible = "allwinner,sun20i-d1-tcon-top"; + reg = <0x5460000 0x1000>; + clocks = <&ccu CLK_BUS_DPSS_TOP>, + <&ccu CLK_TCON_TV>, + <&ccu CLK_TVE>, + <&ccu CLK_MIPI_DSI>; + clock-names = "bus", "tcon-tv0", "tve0", "dsi"; + clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; + resets = <&ccu RST_BUS_DPSS_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon_top_mixer1>; + }; + }; + + tcon_top_mixer1_out: port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint { + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + }; + }; + }; + + tcon_lcd0: lcd-controller@5461000 { + compatible = "allwinner,sun20i-d1-tcon-lcd"; + reg = <0x5461000 0x1000>; + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON_LCD0>, + <&ccu CLK_TCON_LCD0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON_LCD0>, + <&ccu RST_BUS_LVDS0>; + reset-names = "lcd", "lvds"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_lcd0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; + }; + + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; + }; + }; + + tcon_lcd0_out: port@1 { + reg = <1>; + }; + }; + }; + + tcon_tv0: lcd-controller@5470000 { + compatible = "allwinner,sun20i-d1-tcon-tv"; + reg = <0x5470000 0x1000>; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON_TV>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + reg = <1>; + + tcon_tv0_out_tcon_top_hdmi: endpoint { + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + riscv_wdt: watchdog@6011000 { + compatible = "allwinner,sun20i-d1-wdt"; + reg = <0x6011000 0x20>; + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + }; + + r_ccu: clock-controller@7010000 { + compatible = "allwinner,sun20i-d1-r-ccu"; + reg = <0x7010000 0x400>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_DIV3>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rtc: rtc@7090000 { + compatible = "allwinner,sun20i-d1-rtc", + "allwinner,sun50i-r329-rtc"; + reg = <0x7090000 0x400>; + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_BUS_R_RTC>, + <&osc24M>, + <&r_ccu CLK_R_AHB>; + clock-names = "bus", "hosc", "ahb"; + #clock-cells = <1>; + }; + + plic: interrupt-controller@10000000 { + compatible = "allwinner,sun20i-d1-plic", + "thead,c900-plic"; + reg = <0x10000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu0_intc 9>; + interrupt-controller; + riscv,ndev = <176>; + #address-cells = <0>; + #interrupt-cells = <2>; + }; + }; +};
D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as one HiFi 4 DSP. The SoC is based on a design that additionally contained a pair of Cortex A7's. For that reason, some peripherals are duplicated. This devicetree includes all of the peripherals that already have a documented binding. Signed-off-by: Samuel Holland <samuel@sholland.org> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/allwinner/Makefile | 1 + arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++ 3 files changed, 902 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/Makefile create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi