| Message ID | 20230214164135.17039-7-quic_devipriy@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | Add PCIe support for IPQ9574 | expand |
Hi Devi, On 2/14/2023 10:11 PM, Devi Priya wrote: > Add the clocks needed for enabling PCIe in IPQ9574 > > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c > index b2a2d618a5ec..1bf33d582dc2 100644 > --- a/drivers/clk/qcom/gcc-ipq9574.c > +++ b/drivers/clk/qcom/gcc-ipq9574.c > @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { > }, > }; > > +static struct clk_branch gcc_pcie0_pipe_clk = { > + .halt_reg = 0x28044, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x28044, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_pcie0_pipe_clk", > + .parent_hws = (const struct clk_hw *[]) { > + &pcie0_pipe_clk_src.clkr.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { > .reg = 0x29064, > .clkr = { > @@ -1552,6 +1570,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { > }, > }; > > +static struct clk_branch gcc_pcie1_pipe_clk = { > + .halt_reg = 0x29044, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x29044, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_pcie1_pipe_clk", > + .parent_hws = (const struct clk_hw *[]) { > + &pcie1_pipe_clk_src.clkr.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, Looks like indentation issue for the above hunk. Regards, Sricharan
Hi Devi, On 2/14/2023 10:11 PM, Devi Priya wrote: > Add the clocks needed for enabling PCIe in IPQ9574 > > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c > index b2a2d618a5ec..1bf33d582dc2 100644 > --- a/drivers/clk/qcom/gcc-ipq9574.c > +++ b/drivers/clk/qcom/gcc-ipq9574.c > @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { > }, > }; > > +static struct clk_branch gcc_pcie0_pipe_clk = { > + .halt_reg = 0x28044, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x28044, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_pcie0_pipe_clk", > + .parent_hws = (const struct clk_hw *[]) { > + &pcie0_pipe_clk_src.clkr.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + Also, this patch should come before your phy driver updates. Regards, Sricharan
On 2/17/2023 2:11 PM, Sricharan Ramabadhran wrote: > Hi Devi, > > On 2/14/2023 10:11 PM, Devi Priya wrote: >> Add the clocks needed for enabling PCIe in IPQ9574 >> >> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 76 insertions(+) >> >> diff --git a/drivers/clk/qcom/gcc-ipq9574.c >> b/drivers/clk/qcom/gcc-ipq9574.c >> index b2a2d618a5ec..1bf33d582dc2 100644 >> --- a/drivers/clk/qcom/gcc-ipq9574.c >> +++ b/drivers/clk/qcom/gcc-ipq9574.c >> @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux >> pcie0_pipe_clk_src = { >> }, >> }; >> +static struct clk_branch gcc_pcie0_pipe_clk = { >> + .halt_reg = 0x28044, >> + .halt_check = BRANCH_HALT_DELAY, >> + .clkr = { >> + .enable_reg = 0x28044, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_pcie0_pipe_clk", >> + .parent_hws = (const struct clk_hw *[]) { >> + &pcie0_pipe_clk_src.clkr.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { >> .reg = 0x29064, >> .clkr = { >> @@ -1552,6 +1570,24 @@ static struct clk_regmap_phy_mux >> pcie1_pipe_clk_src = { >> }, >> }; >> +static struct clk_branch gcc_pcie1_pipe_clk = { >> + .halt_reg = 0x29044, >> + .halt_check = BRANCH_HALT_DELAY, >> + .clkr = { >> + .enable_reg = 0x29044, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_pcie1_pipe_clk", >> + .parent_hws = (const struct clk_hw *[]) { >> + &pcie1_pipe_clk_src.clkr.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, > > Looks like indentation issue for the above hunk. Sure, will update this in V2 Best Regards, Devi Priya > > Regards, > Sricharan
On 2/17/2023 2:13 PM, Sricharan Ramabadhran wrote: > Hi Devi, > > On 2/14/2023 10:11 PM, Devi Priya wrote: >> Add the clocks needed for enabling PCIe in IPQ9574 >> >> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 76 insertions(+) >> >> diff --git a/drivers/clk/qcom/gcc-ipq9574.c >> b/drivers/clk/qcom/gcc-ipq9574.c >> index b2a2d618a5ec..1bf33d582dc2 100644 >> --- a/drivers/clk/qcom/gcc-ipq9574.c >> +++ b/drivers/clk/qcom/gcc-ipq9574.c >> @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux >> pcie0_pipe_clk_src = { >> }, >> }; >> +static struct clk_branch gcc_pcie0_pipe_clk = { >> + .halt_reg = 0x28044, >> + .halt_check = BRANCH_HALT_DELAY, >> + .clkr = { >> + .enable_reg = 0x28044, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_pcie0_pipe_clk", >> + .parent_hws = (const struct clk_hw *[]) { >> + &pcie0_pipe_clk_src.clkr.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + > > Also, this patch should come before your phy driver updates. Sure got it, will reorder the patches in V2 > > Regards, > Sricharan > Best Regards, Devi Priya
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index b2a2d618a5ec..1bf33d582dc2 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie0_pipe_clk = { + .halt_reg = 0x28044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x28044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { .reg = 0x29064, .clkr = { @@ -1552,6 +1570,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie1_pipe_clk = { + .halt_reg = 0x29044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x29044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie1_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { .reg = 0x2a064, .clkr = { @@ -1566,6 +1602,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie2_pipe_clk = { + .halt_reg = 0x2a044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2a044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie2_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie2_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { .reg = 0x2b064, .clkr = { @@ -1580,6 +1634,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie3_pipe_clk = { + .halt_reg = 0x2b044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2b044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie3_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie3_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(100000000, P_GPLL0, 8, 0, 0), @@ -3901,9 +3973,13 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr, [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr, [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr, + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr, + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr, + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr, + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,