diff mbox series

[2/7] drm/i915/dp: Check if DSC supports the given output_format

Message ID 20230222053153.3658345-3-suraj.kandpal@intel.com (mailing list archive)
State New, archived
Headers show
Series Enable YCbCr420 format for VDSC | expand

Commit Message

Kandpal, Suraj Feb. 22, 2023, 5:31 a.m. UTC
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Go with DSC only if the given output_format is supported.

v2: Use drm helper to get DSC format support for sink.

v3: remove drm_dp_dsc_compute_bpp.

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

Comments

Shankar, Uma March 8, 2023, 10:55 a.m. UTC | #1
> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: [PATCH 2/7] drm/i915/dp: Check if DSC supports the given output_format
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Go with DSC only if the given output_format is supported.
> 
> v2: Use drm helper to get DSC format support for sink.
> 
> v3: remove drm_dp_dsc_compute_bpp.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index fe98c7dec193..f2fb3ec2dd99 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1491,6 +1491,31 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
>  	return drm_dsc_compute_rc_parameters(vdsc_cfg);
>  }
> 
> +static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
> +					 enum intel_output_format output_format)
> {
> +	u8 sink_dsc_format;
> +
> +	switch (output_format) {
> +	case INTEL_OUTPUT_FORMAT_RGB:
> +		sink_dsc_format = DP_DSC_RGB;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR444:
> +		sink_dsc_format = DP_DSC_YCbCr444;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR420:
> +		if (min(intel_dp_source_dsc_version_minor(intel_dp),
> +			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
> +			return false;
> +		sink_dsc_format = DP_DSC_YCbCr420_Native;
> +		break;
> +	default:
> +		return false;
> +	}
> +
> +	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +sink_dsc_format); }
> +
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config,
>  				struct drm_connector_state *conn_state, @@ -
> 1511,6 +1536,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return -EINVAL;
> 
> +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> +		return -EINVAL;
> +
>  	if (compute_pipe_bpp)
>  		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> >max_requested_bpc);
>  	else
> --
> 2.25.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fe98c7dec193..f2fb3ec2dd99 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1491,6 +1491,31 @@  static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	return drm_dsc_compute_rc_parameters(vdsc_cfg);
 }
 
+static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
+					 enum intel_output_format output_format)
+{
+	u8 sink_dsc_format;
+
+	switch (output_format) {
+	case INTEL_OUTPUT_FORMAT_RGB:
+		sink_dsc_format = DP_DSC_RGB;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		sink_dsc_format = DP_DSC_YCbCr444;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		if (min(intel_dp_source_dsc_version_minor(intel_dp),
+			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
+			return false;
+		sink_dsc_format = DP_DSC_YCbCr420_Native;
+		break;
+	default:
+		return false;
+	}
+
+	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
+}
+
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config,
 				struct drm_connector_state *conn_state,
@@ -1511,6 +1536,9 @@  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return -EINVAL;
 
+	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+		return -EINVAL;
+
 	if (compute_pipe_bpp)
 		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
 	else