| Message ID | 20230221024645.127922-1-hal.feng@starfivetech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC | expand |
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Tue, 21 Feb 2023 10:46:26 +0800 you wrote: > This patch series adds basic clock, reset & DT support for StarFive > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings > of VisionFive 2 board and JH7110 SoC. > > You can simply review or test the patches at the link [3]. > > [...] Here is the summary with links: - [v4,01/19] clk: starfive: Factor out common JH7100 and JH7110 code (no matching commit) - [v4,02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h https://git.kernel.org/riscv/c/f3af3b0039fe - [v4,03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code (no matching commit) - [v4,04/19] reset: Create subdirectory for StarFive drivers (no matching commit) - [v4,05/19] reset: starfive: Factor out common JH71X0 reset code (no matching commit) - [v4,06/19] reset: starfive: Extract the common JH71X0 reset code (no matching commit) - [v4,07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code (no matching commit) - [v4,08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers (no matching commit) - [v4,09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator (no matching commit) - [v4,10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator (no matching commit) - [v4,11/19] clk: starfive: Add StarFive JH7110 system clock driver (no matching commit) - [v4,12/19] clk: starfive: Add StarFive JH7110 always-on clock driver (no matching commit) - [v4,13/19] reset: starfive: Add StarFive JH7110 reset driver (no matching commit) - [v4,14/19] dt-bindings: timer: Add StarFive JH7110 clint (no matching commit) - [v4,15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic (no matching commit) - [v4,16/19] dt-bindings: riscv: Add SiFive S7 compatible (no matching commit) - [v4,17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree (no matching commit) - [v4,18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions (no matching commit) - [v4,19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree (no matching commit) You are awesome, thank you!
On Wed, Feb 22, 2023 at 03:00:21PM +0000, patchwork-bot+linux-riscv@kernel.org wrote: > Hello: > > This series was applied to riscv/linux.git (for-next) > by Palmer Dabbelt <palmer@rivosinc.com>: > > On Tue, 21 Feb 2023 10:46:26 +0800 you wrote: > > This patch series adds basic clock, reset & DT support for StarFive > > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl > > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings > > of VisionFive 2 board and JH7110 SoC. > > > > You can simply review or test the patches at the link [3]. > > > > [...] > > Here is the summary with links: > - [v4,01/19] clk: starfive: Factor out common JH7100 and JH7110 code > (no matching commit) > - [v4,02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h > https://git.kernel.org/riscv/c/f3af3b0039fe This pwbot email is wrong, this commit is actually: Merge patch series "riscv: improve link and support ARCH_WANT_LD_ORPHAN_WARN" > - [v4,03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code > (no matching commit) > - [v4,04/19] reset: Create subdirectory for StarFive drivers > (no matching commit) > - [v4,05/19] reset: starfive: Factor out common JH71X0 reset code > (no matching commit) > - [v4,06/19] reset: starfive: Extract the common JH71X0 reset code > (no matching commit) > - [v4,07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code > (no matching commit) > - [v4,08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers > (no matching commit) > - [v4,09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator > (no matching commit) > - [v4,10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator > (no matching commit) > - [v4,11/19] clk: starfive: Add StarFive JH7110 system clock driver > (no matching commit) > - [v4,12/19] clk: starfive: Add StarFive JH7110 always-on clock driver > (no matching commit) > - [v4,13/19] reset: starfive: Add StarFive JH7110 reset driver > (no matching commit) > - [v4,14/19] dt-bindings: timer: Add StarFive JH7110 clint > (no matching commit) > - [v4,15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic > (no matching commit) > - [v4,16/19] dt-bindings: riscv: Add SiFive S7 compatible > (no matching commit) > - [v4,17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree > (no matching commit) > - [v4,18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions > (no matching commit) > - [v4,19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree > (no matching commit) > > You are awesome, thank you! > -- > Deet-doot-dot, I am a bot. > https://korg.docs.kernel.org/patchwork/pwbot.html > >
Hello Hal,
I start to play with jh7110-starfive-visionfive-2-v1.3b I have collect
your series [3]. Now I'm trying to boot the image with the following
cmds:
setenv bootfile vmlinuz;
setenv fileaddr a0000000;
setenv fdtcontroladdr 0xffffffffffffffff;
setenv ipaddr 10.0.0.100;
setenv serverip 10.0.0.1;
setenv kernel_comp_addr_r 0xb0000000;
setenv kernel_comp_size 0x10000000;
tftpboot ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb;
tftpboot ${kernel_addr_r} Image.gz;
run chipa_set_linux;
booti ${kernel_addr_r} - ${fdt_addr_r}
This the result:
Bytes transferred = 109443584 (685fa00 hex)
StarFive # run chipa_set_linux;
StarFive # printenv file
fileaddr filesize
StarFive # printenv filesize
filesize=685fa00
StarFive # booti ${kernel_addr_r} - ${fdt_addr_r}
Uncompressing Kernel Image
## Flattened Device Tree blob at 46000000
Booting using the fdt blob at 0x46000000
Using Device Tree in place at 0000000046000000, end 0000000046005c14
Starting kernel ...
clk u5_dw_i2c_clk_core already disabled
clk u5_dw_i2c_clk_apb already disabled
---------------------------------------------
I'm missing something? Any hints?
Many thanks in advance! :)
Regards,
Tommaso
On Tue, Feb 21, 2023 at 10:46:26AM +0800, Hal Feng wrote:
> This patch series adds basic clock, reset & DT support for StarFive
> JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
> dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
> of VisionFive 2 board and JH7110 SoC.
>
> You can simply review or test the patches at the link [3].
>
> [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/
> [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/
> [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
>
> Changes since v3:
> - Suggested by Conor, Merged clock & reset series and DT series together
> so that they could go via the same tree as the dt-binding headers are
> required by both driver & devicetree.
> - Rebased on tag v6.2.
>
> [Clock & reset]
> Patch 2:
> - Split patch 2 into two. One for renaming file and one for renaming
> variables. (by Conor)
> Patch 4:
> - Split patch 4 into two. One for code movement and one for
> extraction. (by Conor)
> Patch 5 & 9 & 10 & 11:
> - Fixed the issues reported by kernel test robot.
> Patch 9:
> - Set (&priv->base) as driver data instead of (priv->base).
> - Set the frequency of clock PLL0 as 1000MHz for Synchronizing with the
> lastest u-boot setting from StarFive. (by Emil)
> - Used devm_kzalloc() instead of kzalloc() when registering aux device.
> Patch 10:
> - Set (&priv->base) as driver data instead of (priv->base).
> Patch 11:
> - Used (*base) to get the register base address instead of (base).
>
> [Device tree]
> - Dropped patch 1, 4, 5 because they were accepted.
> - Added a new patch to add SiFive S7 compatible. (by Conor)
> - Added a new patch to add JH7110 pin function definitions.
> Patch 6:
> - Changed the label "S76_0" to "S7_0" and used compatible "sifive,s7"
> for core 0.
> - Updated ISA of each cores. (by Conor)
> - Made the node names generic. (by Krzysztof)
> - Added clock-output-names for all external clocks.
> - Added i2c0~6 nodes.
> - Changed the node name "gpio" to "pinctrl". Changed the label "gpio"
> and "gpioa" to "sysgpio" and "aongpio". (by Conor)
> Patch 7:
> - Separated the long lines into more lines in Makefile. (by Conor)
> - Renamed jh7110-starfive-visionfive-2-va.dts and
> jh7110-starfive-visionfive-2-vb.dts to
> jh7110-starfive-visionfive-2-v1.2a.dts and
> jh7110-starfive-visionfive-2-v1.3b.dts.
> Changed the model and compatible to match v1.2A and v1.3B which
> are printed on the silkscreen of VisionFive 2 board. (by Emil)
> - Configured pins for i2c0/2/5/6 and enabled them.
>
> clock & reset v3: https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/
> DT v3: https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
>
> Changes since v2:
> [Clock & reset]
> - Rebased on tag v6.1.
> - Added "JH71X0" to the StarFive driver headers in MAINTAINERS.
> - Removed Co-developed-by tag of Hal in patch 1 and patch 4.
> - Changed the commit author from Hal to Emil in patch 2 and patch 5.
> Removed Co-developed-by tag of Emil in patch 2 and patch 5. (by Emil)
> - Improved the coding style of patch 11, 12 and 13.
> - Dropped patch 14. (by Emil)
> Patch 4:
> - Passed the "owner" member of reset_controller_dev structure
> directly in reset_starfive_jh7100_register(). (by Emil)
> - Added MAINTAINERS changes.
> Patch 7:
> - Split patch 7 into sys part and aon part. Merged them into patch 9 and
> patch 10 respectively. (by Krzysztof)
> - Renamed include/dt-bindings/clock/starfive-jh7110.h to
> include/dt-bindings/clock/starfive,jh7110-crg.h. (by Krzysztof)
> - Synchronized the definitions with the latest changes from Emil.
> Patch 8:
> - Split patch 8 into sys part and aon part. Merged them into patch 9 and
> patch 10 respectively. (by Krzysztof)
> - Renamed include/dt-bindings/reset/starfive-jh7110.h to
> include/dt-bindings/reset/starfive,jh7110-crg.h. (by Krzysztof)
> - Fixed the date of Copyright. (by Emil)
> - Dropped weird indentations. (by Krzysztof)
> - Synchronized the definitions with the latest changes from Emil.
> Patch 9:
> - Improved the description of clocks. (by Emil and Krzysztof)
> - Added MAINTAINERS changes.
> Patch 10:
> - Improved the description of clocks. (by Emil and Krzysztof)
> - Changed the clock-name "clk_rtc" to "rtc_osc" and "apb_bus_func" to
> "apb_bus".
> Patch 11:
> - Removed the flags of trace/debug clocks and set the flags of core clocks
> as CLK_IS_CRITICAL. (by Emil)
> - Deleted the extra 1-1 clocks and synchronized the clock tree with the
> latest changes from Emil. (by Emil)
> - Selected RESET_STARFIVE_JH7110 in Kconfig option CLK_STARFIVE_JH7110_SYS.
> Patch 12:
> - Changed the macro JH7110_AONCLK_RTC to JH7110_AONCLK_RTC_OSC and
> JH7110_AONCLK_APB_BUS_FUNC to JH7110_AONCLK_APB_BUS.
> - Synchronized the clock tree with the latest changes from Emil.
> - Set the MODULE_LICENSE as "GPL" according to commit bf7fbeeae6db.
> Patch 13:
> - Removed the "asserted" member in reset_info structure and always pass
> NULL when calling reset_starfive_jh71x0_register(). (by Emil)
>
> [Device tree]
> - Rebased on tag v6.1.
> - Dropped patch 8 because it was merged.
> Patch 1:
> - Made the links into "Link:" tags. (by Conor)
> - Corrected the board name to "VisionFive 2" instead of
> "VisionFive V2" and added compatibles for version A and
> version B of VisionFive 2. (by Emil)
> Patch 4:
> - Used "sifive,ccache0" compatible string to match. (by Conor)
> Patch 5:
> - Dropped "select SIFIVE_CCACHE" in config SOC_STARFIVE. (by Conor)
> - Dropped "starfive,jh7110-ccache" compatible in
> drivers/soc/sifive/sifive_ccache.c.
> Patch 6:
> - Removed all "clock-frequency = <0>". (by Conor)
> - Sorted the nodes after their addresses. (by Emil)
> - Renamed "clk_rtc" to "rtc_osc".
> - Added "sifive,ccache0" compatible in the cache-controller node.
> - Renamed "JH7110_SYSCLK_APB_BUS_FUNC" to "JH7110_SYSCLK_APB_BUS" and
> renamed "apb_bus_func" to "apb_bus".
> Renamed "JH7110_SYSCLK_IOMUX" to "JH7110_SYSCLK_IOMUX_APB".
> Renamed "JH7110_SYSRST_IOMUX" to "JH7110_SYSRST_IOMUX_APB".
> Renamed "JH7110_AONRST_AON_IOMUX" to "JH7110_AONRST_IOMUX".
> - Removed "reg-names" in gpio nodes.
> Patch 7:
> - Corrected the board name to "VisionFive 2" instead of "VisionFive V2".
> - Renamed jh7110-starfive-visionfive-v2.dts to
> jh7110-starfive-visionfive-2.dtsi.
> - Added dts for VisionFive 2 version A and version B boards.
> - In the chosen node, deleted "linux,initrd-start" and "linux,initrd-end"
> and changed the value of "stdout-path" to "serial0:115200n8".
> - Changed the bias of uart0 "rx-pins" to
> "bias-disable; /* external pull-up */".
> - Renamed "clk_rtc" to "rtc_osc".
> - Moved the gpio node behind the uart0 node.
>
> clock & reset v2: https://lore.kernel.org/all/20221118010627.70576-1-hal.feng@starfivetech.com/
> DT v2: https://lore.kernel.org/all/20221118011714.70877-1-hal.feng@starfivetech.com/
>
> Changes since v1:
> [Clock & reset]
> - Rebased on tag v6.1-rc5.
> - Rewrote the clock and reset drivers using auxiliary bus framework, so
> patch 8, 9, 15 were dropped and all patches changed a lot. (by Stephen)
> - Split Patch 14 into two patches. One is for factoring out the common
> JH71X0 code, the another one is for renaming. (by Stephen)
> - Created a subdirectory for StarFive reset drivers.
> - Factored out common JH71X0 reset code.
> - Renamed the common clock and reset code from "*starfive*" or
> "*STARFIVE*" to "*jh71x0*" or "*JH71X0*".
> - Combined JH7110 system and always-on clock DT binding headers in one
> file named "include/dt-bindings/clock/starfive-jh7110.h".
> - Renamed clock definitions "JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK" and
> "JH7110_SYSCLK_U2_PCLK_MUX_PCLK" to "JH7110_SYSCLK_PCLK2_MUX_FUNC" and
> "JH7110_SYSCLK_PCLK2_MUX".
> - Rewrote the DT bindings of clock and reset for using auxiliary bus.
> - Registered an auxiliary device for reset controller in clock drivers.
> - Changed clock names "CODAJ*" and "WAVE*" to "codaj*" and "wave*".
> Changed clock names "u2_pclk_mux_func_pclk" and "u2_pclk_mux_pclk" to
> "pclk2_mux_func" and "pclk2_mux".
> - Changed the flags of clock apb0 and noc_bus_isp_axi to CLK_IS_CRITICAL
> as suggested by StarFive SDK group.
> - Registered clock gmac0_gtxc as a gate clock instead of a div clock
> as suggested by StarFive SDK group.
> - Changed the frequency of clock pll2_out to 1188MHz as suggested by
> StarFive SDK group.
> - Fixed the bug that the clock JH7110_AONCLK_GMAC0_GTXCLK was not handled
> in JH7110 always-on clock driver.
> - Registered the reset driver as an auxiliary driver.
> - Reworded the commit messages.
>
> [Device tree]
> - Rebased on tag v6.1-rc5.
> - Added blank line in patch 1. (by Krzysztof)
> - Rebased patch 4 and 6 on the newest code. (by Conor)
> - Dropped patch 5. (by Conor)
> - Removed the quirk of JH7100 in patch 6, considering this patch series
> should only add support for JH7110.
> - For patch 27, added Co-developed-by tag for Jianlong and me. Renamed
> cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style
> of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts.
> Rewrote clock-controller nodes and deleted reset-controller nodes for
> using auxiliary bus. Rewrote gpio nodes following generic pinctrl
> bindings. Removed the redundant second reset entry of uart nodes.
> - For patch 28, added Co-developed-by tag for Jianlong and me. Added a
> chosen node. Removed reserved-memory node. Added fixed frequency clock
> nodes for overriding the "clock-frequency" properties. Rewrote the gpio
> nodes following generic pinctrl bindings.
> - Dropped patch 30. (by Conor)
> - Reworded the commit messages.
>
> v1: https://lore.kernel.org/all/20220929143225.17907-1-hal.feng@linux.starfivetech.com/
>
> Emil Renner Berthing (16):
> clk: starfive: Factor out common JH7100 and JH7110 code
> clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
> clk: starfive: Rename "jh7100" to "jh71x0" for the common code
> reset: Create subdirectory for StarFive drivers
> reset: starfive: Factor out common JH71X0 reset code
> reset: starfive: Extract the common JH71X0 reset code
> reset: starfive: Rename "jh7100" to "jh71x0" for the common code
> reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
> dt-bindings: clock: Add StarFive JH7110 system clock and reset
> generator
> dt-bindings: clock: Add StarFive JH7110 always-on clock and reset
> generator
> clk: starfive: Add StarFive JH7110 system clock driver
> clk: starfive: Add StarFive JH7110 always-on clock driver
> dt-bindings: timer: Add StarFive JH7110 clint
> dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> riscv: dts: starfive: Add initial StarFive JH7110 device tree
> riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
> tree
>
> Hal Feng (2):
> reset: starfive: Add StarFive JH7110 reset driver
> dt-bindings: riscv: Add SiFive S7 compatible
>
> Jianlong Huang (1):
> riscv: dts: starfive: Add StarFive JH7110 pin function definitions
>
> .../clock/starfive,jh7110-aoncrg.yaml | 76 ++
> .../clock/starfive,jh7110-syscrg.yaml | 80 ++
> .../sifive,plic-1.0.0.yaml | 1 +
> .../devicetree/bindings/riscv/cpus.yaml | 1 +
> .../bindings/timer/sifive,clint.yaml | 1 +
> MAINTAINERS | 16 +-
> arch/riscv/boot/dts/starfive/Makefile | 6 +-
> arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++++
> .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 +
> .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 +
> .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 507 +++++++++++++
> drivers/clk/starfive/Kconfig | 27 +
> drivers/clk/starfive/Makefile | 6 +-
> .../clk/starfive/clk-starfive-jh7100-audio.c | 74 +-
> drivers/clk/starfive/clk-starfive-jh7100.c | 713 +++++-------------
> drivers/clk/starfive/clk-starfive-jh7100.h | 112 ---
> .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++
> .../clk/starfive/clk-starfive-jh7110-sys.c | 448 +++++++++++
> drivers/clk/starfive/clk-starfive-jh71x0.c | 383 ++++++++++
> drivers/clk/starfive/clk-starfive-jh71x0.h | 122 +++
> drivers/reset/Kconfig | 8 +-
> drivers/reset/Makefile | 2 +-
> drivers/reset/reset-starfive-jh7100.c | 173 -----
> drivers/reset/starfive/Kconfig | 20 +
> drivers/reset/starfive/Makefile | 5 +
> .../reset/starfive/reset-starfive-jh7100.c | 74 ++
> .../reset/starfive/reset-starfive-jh7110.c | 64 ++
> .../reset/starfive/reset-starfive-jh71x0.c | 131 ++++
> .../reset/starfive/reset-starfive-jh71x0.h | 20 +
> .../dt-bindings/clock/starfive,jh7110-crg.h | 225 ++++++
> .../dt-bindings/reset/starfive,jh7110-crg.h | 154 ++++
> 32 files changed, 3296 insertions(+), 858 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
> create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
> create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
> delete mode 100644 drivers/reset/reset-starfive-jh7100.c
> create mode 100644 drivers/reset/starfive/Kconfig
> create mode 100644 drivers/reset/starfive/Makefile
> create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.c
> create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
> create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c
> create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
> create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
> create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
>
>
> base-commit: c9c3395d5e3dcc6daee66c6908354d47bf98cb0c
> --
> 2.38.1
>
On Fri, 3 Mar 2023 20:08:20 +0100, Tommaso Merciai wrote: > Hello Hal, > I start to play with jh7110-starfive-visionfive-2-v1.3b I have collect > your series [3]. Now I'm trying to boot the image with the following > cmds: > > setenv bootfile vmlinuz; > setenv fileaddr a0000000; > setenv fdtcontroladdr 0xffffffffffffffff; > setenv ipaddr 10.0.0.100; > setenv serverip 10.0.0.1; > setenv kernel_comp_addr_r 0xb0000000; > setenv kernel_comp_size 0x10000000; > tftpboot ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb; > tftpboot ${kernel_addr_r} Image.gz; > run chipa_set_linux; > booti ${kernel_addr_r} - ${fdt_addr_r} > > > This the result: > > Bytes transferred = 109443584 (685fa00 hex) > StarFive # run chipa_set_linux; > StarFive # printenv file > fileaddr filesize > StarFive # printenv filesize > filesize=685fa00 > StarFive # booti ${kernel_addr_r} - ${fdt_addr_r} > Uncompressing Kernel Image > ## Flattened Device Tree blob at 46000000 > Booting using the fdt blob at 0x46000000 > Using Device Tree in place at 0000000046000000, end 0000000046005c14 > > Starting kernel ... > > clk u5_dw_i2c_clk_core already disabled > clk u5_dw_i2c_clk_apb already disabled > > --------------------------------------------- > > I'm missing something? Any hints? > Many thanks in advance! :) You can try the instructions at the link [1]. The branch [1] is based on v2 of this series, so you need to change the dtb name to "jh7110-starfive-visionfive-2-v1.3b.dtb" when using tftpboot. I will send v5 and update it to [1] this week. [1] https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_upstream Best regards, Hal
Hi Hal, On Mon, Mar 06, 2023 at 11:29:48AM +0800, Hal Feng wrote: > On Fri, 3 Mar 2023 20:08:20 +0100, Tommaso Merciai wrote: > > Hello Hal, > > I start to play with jh7110-starfive-visionfive-2-v1.3b I have collect > > your series [3]. Now I'm trying to boot the image with the following > > cmds: > > > > setenv bootfile vmlinuz; > > setenv fileaddr a0000000; > > setenv fdtcontroladdr 0xffffffffffffffff; > > setenv ipaddr 10.0.0.100; > > setenv serverip 10.0.0.1; > > setenv kernel_comp_addr_r 0xb0000000; > > setenv kernel_comp_size 0x10000000; > > tftpboot ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb; > > tftpboot ${kernel_addr_r} Image.gz; > > run chipa_set_linux; > > booti ${kernel_addr_r} - ${fdt_addr_r} > > > > > > This the result: > > > > Bytes transferred = 109443584 (685fa00 hex) > > StarFive # run chipa_set_linux; > > StarFive # printenv file > > fileaddr filesize > > StarFive # printenv filesize > > filesize=685fa00 > > StarFive # booti ${kernel_addr_r} - ${fdt_addr_r} > > Uncompressing Kernel Image > > ## Flattened Device Tree blob at 46000000 > > Booting using the fdt blob at 0x46000000 > > Using Device Tree in place at 0000000046000000, end 0000000046005c14 > > > > Starting kernel ... > > > > clk u5_dw_i2c_clk_core already disabled > > clk u5_dw_i2c_clk_apb already disabled > > > > --------------------------------------------- > > > > I'm missing something? Any hints? > > Many thanks in advance! :) > > You can try the instructions at the link [1]. The branch [1] is > based on v2 of this series, so you need to change the dtb name > to "jh7110-starfive-visionfive-2-v1.3b.dtb" when using tftpboot. > I will send v5 and update it to [1] this week. > > [1] https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_upstream Thanks for your help! Collecting your latest 26 patches from [1] I'm able to boot the board using cmds suggested in your link [2]. In particular I pick the following patches from your repo: 11934a315b67 (HEAD -> visionfive2-minimal, tag: visionfive2-minimal-v4, origin/visionfive2-minimal) riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree c246291ed2d0 riscv: dts: starfive: Add StarFive JH7110 pin function definitions 53c360e87ee8 riscv: dts: starfive: Add initial StarFive JH7110 device tree e769528b7cd8 dt-bindings: riscv: Add SiFive S7 compatible 1f4c7408d02a soc: sifive: ccache: Add StarFive JH7110 support cd1a430b56db dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC 96fcf2e390d3 dt-bindings: interrupt-controller: Add StarFive JH7110 plic 542c43452e08 dt-bindings: timer: Add StarFive JH7110 clint 2b1bb27b0cff dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board 328cac9205d2 pinctrl: starfive: Add StarFive JH7110 aon controller driver dd082f89c4fb pinctrl: starfive: Add StarFive JH7110 sys controller driver aabf6ba76b81 dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl f2c5025c54f9 dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl 7601624bdde0 reset: starfive: Add StarFive JH7110 reset driver b1a2db0b97f4 clk: starfive: Add StarFive JH7110 always-on clock driver 0b2aaa26d5c8 clk: starfive: Add StarFive JH7110 system clock driver 2959b29a7d80 dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator cfb65ad0957a dt-bindings: clock: Add StarFive JH7110 system clock and reset generator f9df80901f49 reset: starfive: jh71x0: Use 32bit I/O on 32bit registers c9400fc69d3a reset: starfive: Rename "jh7100" to "jh71x0" for the common code 8f05fdea85cd reset: starfive: Extract the common JH71X0 reset code 28f5efaa3b06 reset: starfive: Factor out common JH71X0 reset code aa82ce33f593 reset: Create subdirectory for StarFive drivers fb87b93f6aa8 clk: starfive: Rename "jh7100" to "jh71x0" for the common code d73e36277d5f clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h 04611bf6db16 clk: starfive: Factor out common JH7100 and JH7110 code Hope this can help other peoples that start to play with jh7110-starfive-visionfive-2-v1.3b :) Thanks for your work! Regards, Tommaso [1] https://github.com/hal-feng/linux/commits/visionfive2-minimal [2] https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_upstream > > Best regards, > Hal
On Tue, 21 Feb 2023 10:46:26 +0800, Hal Feng wrote: > This patch series adds basic clock, reset & DT support for StarFive > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings > of VisionFive 2 board and JH7110 SoC. > > You can simply review or test the patches at the link [3]. > > [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/ > [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/ > [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal Hi Conor, When I tried to rebase these patches on v6.3-rc1, I found the kernel would crash on the VisionFive 2 board during startup. The logs are as below. I checkout the branch to the mainline and found that the kernel would also crash on the VisionFive board which is equipped with JH7100 SoC. -------------------------------- Unable to handle kernel paging request at virtual address 0000004cccccccd4 Oops [#1] Modules linked in: CPU: 3 PID: 87 Comm: udevd Not tainted 6.3.0-rc1-00019-g239e7809f291 #305 Hardware name: StarFive VisionFive 2 v1.3B (DT) epc : enqueue_timer+0x18/0x90 ra : internal_add_timer+0x2c/0x38 epc : ffffffff8006a714 ra : ffffffff8006a7b8 sp : ffffffc80443bc80 gp : ffffffff80eb5100 tp : ffffffd8c01db200 t0 : 0000000000000000 t1 : 000000000000000f t2 : 0000000038b3ea28 s0 : ffffffc80443bcb0 s1 : ffffffff80813940 a0 : ffffffff80813940 a1 : ffffffc80443bd48 a2 : 000000000000020b a3 : cccccccd0b000000 a4 : cccccccccccccccc a5 : 000000000000020b a6 : ffffffff80814a08 a7 : 0000000000000001 s2 : ffffffc80443bd48 s3 : 0000000008400040 s4 : ffffffff80813940 s5 : ffffffff80eea0b8 s6 : ffffffff80eb7220 s7 : 0000000000000040 s8 : ffffffff80eb61e0 s9 : 0000002ac84a2548 s10: 0000002ad53e92c0 s11: 0000000000000001 t3 : 000000000000003f t4 : 0000000000000000 t5 : 0000000000000004 t6 : 0000000000000003 status: 0000000200000100 badaddr: 0000004cccccccd4 cause: 000000000000000f [<ffffffff8006a714>] enqueue_timer+0x18/0x90 [<ffffffff8006aa64>] add_timer_on+0xf0/0x134 [<ffffffff80500f18>] try_to_generate_entropy+0x1ec/0x232 [<ffffffff8035a636>] urandom_read_iter+0x42/0xc2 [<ffffffff800fff16>] vfs_read+0x17c/0x1e4 [<ffffffff801005b6>] ksys_read+0x78/0x98 [<ffffffff801005e4>] sys_read+0xe/0x16 [<ffffffff800035dc>] ret_from_syscall+0x0/0x2 Code: 9381 9713 0037 0813 0705 983a 3703 0008 e198 c311 (e70c) d713 ---[ end trace 0000000000000000 ]--- note: udevd[87] exited with irqs disabled Segmentation fault FAIL Saving random seed: rcu: INFO: rcu_sched detected stalls on CPUs/tasks: rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=7474 rcu: (detected by 2, t=15005 jiffies, g=-195, q=35 ncpus=4) Task dump for CPU 1: task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008 Call Trace: [<ffffffff80003764>] ret_from_fork+0x0/0xc rcu: INFO: rcu_sched detected stalls on CPUs/tasks: rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=29814 rcu: (detected by 2, t=60018 jiffies, g=-195, q=35 ncpus=4) Task dump for CPU 1: task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008 Call Trace: [<ffffffff80003764>] ret_from_fork+0x0/0xc ... -------------------------------- I used 'git bisect' and found out the commit 9493e6f3ce02 is the cause. I tried to revert this commit on the tag v6.3-rc1, but it seems there is no improvement. Any options I am missing? Could you please give me some suggestions to adapt to the new changes between 6.2 and 6.3? Thank you in advance. Best regards, Hal
On Tue, Mar 07, 2023 at 04:36:41PM +0800, Hal Feng wrote: > On Tue, 21 Feb 2023 10:46:26 +0800, Hal Feng wrote: > > This patch series adds basic clock, reset & DT support for StarFive > > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl > > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings > > of VisionFive 2 board and JH7110 SoC. > > > > You can simply review or test the patches at the link [3]. > > > > [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/ > > [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/ > > [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal > > Hi Conor, > > When I tried to rebase these patches on v6.3-rc1, I found the kernel > would crash on the VisionFive 2 board during startup. The logs are as > below. I checkout the branch to the mainline and found that the kernel > would also crash on the VisionFive board which is equipped with JH7100 > SoC. > > -------------------------------- > Unable to handle kernel paging request at virtual address 0000004cccccccd4 > Oops [#1] > Modules linked in: > CPU: 3 PID: 87 Comm: udevd Not tainted 6.3.0-rc1-00019-g239e7809f291 #305 > Hardware name: StarFive VisionFive 2 v1.3B (DT) > epc : enqueue_timer+0x18/0x90 > ra : internal_add_timer+0x2c/0x38 > epc : ffffffff8006a714 ra : ffffffff8006a7b8 sp : ffffffc80443bc80 > gp : ffffffff80eb5100 tp : ffffffd8c01db200 t0 : 0000000000000000 > t1 : 000000000000000f t2 : 0000000038b3ea28 s0 : ffffffc80443bcb0 > s1 : ffffffff80813940 a0 : ffffffff80813940 a1 : ffffffc80443bd48 > a2 : 000000000000020b a3 : cccccccd0b000000 a4 : cccccccccccccccc > a5 : 000000000000020b a6 : ffffffff80814a08 a7 : 0000000000000001 > s2 : ffffffc80443bd48 s3 : 0000000008400040 s4 : ffffffff80813940 > s5 : ffffffff80eea0b8 s6 : ffffffff80eb7220 s7 : 0000000000000040 > s8 : ffffffff80eb61e0 s9 : 0000002ac84a2548 s10: 0000002ad53e92c0 > s11: 0000000000000001 t3 : 000000000000003f t4 : 0000000000000000 > t5 : 0000000000000004 t6 : 0000000000000003 > status: 0000000200000100 badaddr: 0000004cccccccd4 cause: 000000000000000f > [<ffffffff8006a714>] enqueue_timer+0x18/0x90 > [<ffffffff8006aa64>] add_timer_on+0xf0/0x134 > [<ffffffff80500f18>] try_to_generate_entropy+0x1ec/0x232 > [<ffffffff8035a636>] urandom_read_iter+0x42/0xc2 > [<ffffffff800fff16>] vfs_read+0x17c/0x1e4 > [<ffffffff801005b6>] ksys_read+0x78/0x98 > [<ffffffff801005e4>] sys_read+0xe/0x16 > [<ffffffff800035dc>] ret_from_syscall+0x0/0x2 > Code: 9381 9713 0037 0813 0705 983a 3703 0008 e198 c311 (e70c) d713 > ---[ end trace 0000000000000000 ]--- > note: udevd[87] exited with irqs disabled > Segmentation fault > FAIL > Saving random seed: > rcu: INFO: rcu_sched detected stalls on CPUs/tasks: > rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=7474 > rcu: (detected by 2, t=15005 jiffies, g=-195, q=35 ncpus=4) > Task dump for CPU 1: > task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008 > Call Trace: > [<ffffffff80003764>] ret_from_fork+0x0/0xc > rcu: INFO: rcu_sched detected stalls on CPUs/tasks: > rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=29814 > rcu: (detected by 2, t=60018 jiffies, g=-195, q=35 ncpus=4) > Task dump for CPU 1: > task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008 > Call Trace: > [<ffffffff80003764>] ret_from_fork+0x0/0xc > ... > -------------------------------- > > I used 'git bisect' and found out the commit 9493e6f3ce02 is the > cause. I tried to revert this commit on the tag v6.3-rc1, but it > seems there is no improvement. Hmm, I'm not entirely sure that that is a good bisect. This is a fix for my stupidity in the commit you mention: https://lore.kernel.org/linux-riscv/20230302174154.970746-1-conor@kernel.org/ But the main backtrace there is not from that patch at all, I think it is Linus' fault. The HEAD of Linus' tree is currently 8ca09d5fa3549 ("cpumask: fix incorrect cpumask scanning result checks") should be a fix for the backtrace that you are seeing above. > Any options I am missing? Could you please give me some suggestions > to adapt to the new changes between 6.2 and 6.3? Thank you in > advance. LMK if the above two things don't fix it for you & I'll go digging tonight. Cheers, Conor.
On Tue, 7 Mar 2023 08:51:49 +0000, Conor Dooley wrote: > On Tue, Mar 07, 2023 at 04:36:41PM +0800, Hal Feng wrote: >> On Tue, 21 Feb 2023 10:46:26 +0800, Hal Feng wrote: >> > This patch series adds basic clock, reset & DT support for StarFive >> > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl >> > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings >> > of VisionFive 2 board and JH7110 SoC. >> > >> > You can simply review or test the patches at the link [3]. >> > >> > [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/ >> > [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/ >> > [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal >> >> Hi Conor, >> >> When I tried to rebase these patches on v6.3-rc1, I found the kernel >> would crash on the VisionFive 2 board during startup. The logs are as >> below. I checkout the branch to the mainline and found that the kernel >> would also crash on the VisionFive board which is equipped with JH7100 >> SoC. >> >> -------------------------------- >> Unable to handle kernel paging request at virtual address 0000004cccccccd4 >> Oops [#1] >> Modules linked in: >> CPU: 3 PID: 87 Comm: udevd Not tainted 6.3.0-rc1-00019-g239e7809f291 #305 >> Hardware name: StarFive VisionFive 2 v1.3B (DT) >> epc : enqueue_timer+0x18/0x90 >> ra : internal_add_timer+0x2c/0x38 >> epc : ffffffff8006a714 ra : ffffffff8006a7b8 sp : ffffffc80443bc80 >> gp : ffffffff80eb5100 tp : ffffffd8c01db200 t0 : 0000000000000000 >> t1 : 000000000000000f t2 : 0000000038b3ea28 s0 : ffffffc80443bcb0 >> s1 : ffffffff80813940 a0 : ffffffff80813940 a1 : ffffffc80443bd48 >> a2 : 000000000000020b a3 : cccccccd0b000000 a4 : cccccccccccccccc >> a5 : 000000000000020b a6 : ffffffff80814a08 a7 : 0000000000000001 >> s2 : ffffffc80443bd48 s3 : 0000000008400040 s4 : ffffffff80813940 >> s5 : ffffffff80eea0b8 s6 : ffffffff80eb7220 s7 : 0000000000000040 >> s8 : ffffffff80eb61e0 s9 : 0000002ac84a2548 s10: 0000002ad53e92c0 >> s11: 0000000000000001 t3 : 000000000000003f t4 : 0000000000000000 >> t5 : 0000000000000004 t6 : 0000000000000003 >> status: 0000000200000100 badaddr: 0000004cccccccd4 cause: 000000000000000f >> [<ffffffff8006a714>] enqueue_timer+0x18/0x90 >> [<ffffffff8006aa64>] add_timer_on+0xf0/0x134 >> [<ffffffff80500f18>] try_to_generate_entropy+0x1ec/0x232 >> [<ffffffff8035a636>] urandom_read_iter+0x42/0xc2 >> [<ffffffff800fff16>] vfs_read+0x17c/0x1e4 >> [<ffffffff801005b6>] ksys_read+0x78/0x98 >> [<ffffffff801005e4>] sys_read+0xe/0x16 >> [<ffffffff800035dc>] ret_from_syscall+0x0/0x2 >> Code: 9381 9713 0037 0813 0705 983a 3703 0008 e198 c311 (e70c) d713 >> ---[ end trace 0000000000000000 ]--- >> note: udevd[87] exited with irqs disabled >> Segmentation fault >> FAIL >> Saving random seed: >> rcu: INFO: rcu_sched detected stalls on CPUs/tasks: >> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=7474 >> rcu: (detected by 2, t=15005 jiffies, g=-195, q=35 ncpus=4) >> Task dump for CPU 1: >> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008 >> Call Trace: >> [<ffffffff80003764>] ret_from_fork+0x0/0xc >> rcu: INFO: rcu_sched detected stalls on CPUs/tasks: >> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=29814 >> rcu: (detected by 2, t=60018 jiffies, g=-195, q=35 ncpus=4) >> Task dump for CPU 1: >> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008 >> Call Trace: >> [<ffffffff80003764>] ret_from_fork+0x0/0xc >> ... >> -------------------------------- >> >> I used 'git bisect' and found out the commit 9493e6f3ce02 is the >> cause. I tried to revert this commit on the tag v6.3-rc1, but it >> seems there is no improvement. > > Hmm, I'm not entirely sure that that is a good bisect. > This is a fix for my stupidity in the commit you mention: > https://lore.kernel.org/linux-riscv/20230302174154.970746-1-conor@kernel.org/ > > But the main backtrace there is not from that patch at all, I think it > is Linus' fault. > The HEAD of Linus' tree is currently 8ca09d5fa3549 ("cpumask: fix > incorrect cpumask scanning result checks") should be a fix for the > backtrace that you are seeing above. > >> Any options I am missing? Could you please give me some suggestions >> to adapt to the new changes between 6.2 and 6.3? Thank you in >> advance. > > LMK if the above two things don't fix it for you & I'll go digging > tonight. The above two methods can fix the problem. Here are my test results. The VisionFive board can boot up successfully if and only if all above two applied. The VisionFive 2 board can boot up successfully if I merge Linus's new changes. Hope your fix will be merged in rc2. Thank you for your reply. Best regards, Hal
Hello Hal/Conor, On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote: > On Tue, 7 Mar 2023 08:51:49 +0000, Conor Dooley wrote: > > On Tue, Mar 07, 2023 at 04:36:41PM +0800, Hal Feng wrote: > >> On Tue, 21 Feb 2023 10:46:26 +0800, Hal Feng wrote: > >> > This patch series adds basic clock, reset & DT support for StarFive > >> > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl > >> > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings > >> > of VisionFive 2 board and JH7110 SoC. > >> > > >> > You can simply review or test the patches at the link [3]. > >> > > >> > [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/ > >> > [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/ > >> > [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal > >> > >> Hi Conor, > >> > >> When I tried to rebase these patches on v6.3-rc1, I found the kernel > >> would crash on the VisionFive 2 board during startup. The logs are as > >> below. I checkout the branch to the mainline and found that the kernel > >> would also crash on the VisionFive board which is equipped with JH7100 > >> SoC. > >> > >> -------------------------------- > >> Unable to handle kernel paging request at virtual address 0000004cccccccd4 > >> Oops [#1] > >> Modules linked in: > >> CPU: 3 PID: 87 Comm: udevd Not tainted 6.3.0-rc1-00019-g239e7809f291 #305 > >> Hardware name: StarFive VisionFive 2 v1.3B (DT) > >> epc : enqueue_timer+0x18/0x90 > >> ra : internal_add_timer+0x2c/0x38 > >> epc : ffffffff8006a714 ra : ffffffff8006a7b8 sp : ffffffc80443bc80 > >> gp : ffffffff80eb5100 tp : ffffffd8c01db200 t0 : 0000000000000000 > >> t1 : 000000000000000f t2 : 0000000038b3ea28 s0 : ffffffc80443bcb0 > >> s1 : ffffffff80813940 a0 : ffffffff80813940 a1 : ffffffc80443bd48 > >> a2 : 000000000000020b a3 : cccccccd0b000000 a4 : cccccccccccccccc > >> a5 : 000000000000020b a6 : ffffffff80814a08 a7 : 0000000000000001 > >> s2 : ffffffc80443bd48 s3 : 0000000008400040 s4 : ffffffff80813940 > >> s5 : ffffffff80eea0b8 s6 : ffffffff80eb7220 s7 : 0000000000000040 > >> s8 : ffffffff80eb61e0 s9 : 0000002ac84a2548 s10: 0000002ad53e92c0 > >> s11: 0000000000000001 t3 : 000000000000003f t4 : 0000000000000000 > >> t5 : 0000000000000004 t6 : 0000000000000003 > >> status: 0000000200000100 badaddr: 0000004cccccccd4 cause: 000000000000000f > >> [<ffffffff8006a714>] enqueue_timer+0x18/0x90 > >> [<ffffffff8006aa64>] add_timer_on+0xf0/0x134 > >> [<ffffffff80500f18>] try_to_generate_entropy+0x1ec/0x232 > >> [<ffffffff8035a636>] urandom_read_iter+0x42/0xc2 > >> [<ffffffff800fff16>] vfs_read+0x17c/0x1e4 > >> [<ffffffff801005b6>] ksys_read+0x78/0x98 > >> [<ffffffff801005e4>] sys_read+0xe/0x16 > >> [<ffffffff800035dc>] ret_from_syscall+0x0/0x2 > >> Code: 9381 9713 0037 0813 0705 983a 3703 0008 e198 c311 (e70c) d713 > >> ---[ end trace 0000000000000000 ]--- > >> note: udevd[87] exited with irqs disabled > >> Segmentation fault > >> FAIL > >> Saving random seed: > >> rcu: INFO: rcu_sched detected stalls on CPUs/tasks: > >> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=7474 > >> rcu: (detected by 2, t=15005 jiffies, g=-195, q=35 ncpus=4) > >> Task dump for CPU 1: > >> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008 > >> Call Trace: > >> [<ffffffff80003764>] ret_from_fork+0x0/0xc > >> rcu: INFO: rcu_sched detected stalls on CPUs/tasks: > >> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=29814 > >> rcu: (detected by 2, t=60018 jiffies, g=-195, q=35 ncpus=4) > >> Task dump for CPU 1: > >> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008 > >> Call Trace: > >> [<ffffffff80003764>] ret_from_fork+0x0/0xc > >> ... > >> -------------------------------- > >> > >> I used 'git bisect' and found out the commit 9493e6f3ce02 is the > >> cause. I tried to revert this commit on the tag v6.3-rc1, but it > >> seems there is no improvement. > > > > Hmm, I'm not entirely sure that that is a good bisect. > > This is a fix for my stupidity in the commit you mention: > > https://lore.kernel.org/linux-riscv/20230302174154.970746-1-conor@kernel.org/ > > > > But the main backtrace there is not from that patch at all, I think it > > is Linus' fault. > > The HEAD of Linus' tree is currently 8ca09d5fa3549 ("cpumask: fix > > incorrect cpumask scanning result checks") should be a fix for the > > backtrace that you are seeing above. > > > >> Any options I am missing? Could you please give me some suggestions > >> to adapt to the new changes between 6.2 and 6.3? Thank you in > >> advance. > > > > LMK if the above two things don't fix it for you & I'll go digging > > tonight. > > The above two methods can fix the problem. Here are my test results. > The VisionFive board can boot up successfully if and only if all above > two applied. > The VisionFive 2 board can boot up successfully if I merge Linus's new > changes. Tested also on my side. Hope this can be helpfull. > > Hope your fix will be merged in rc2. Thank you for your reply. Fully agree. Regards, Tommaso > > Best regards, > Hal
On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote: > On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote: > > The above two methods can fix the problem. Here are my test results. > > The VisionFive board can boot up successfully if and only if all above > > two applied. > > The VisionFive 2 board can boot up successfully if I merge Linus's new > > changes. > > Tested also on my side. Hope this can be helpfull. > > > Hope your fix will be merged in rc2. Thank you for your reply. > > Fully agree. If you only have a VisionFive 2, it shouldn't matter to you, as you don't need to fix up any SiFive errata (at the moment at least). Linus' fix is already in his tree, so should be in -rc2! The fix for the VisionFive was applied to Palmer's RISC-V fixes tree last night: https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b Thanks, Conor.
On Wed, Mar 08, 2023 at 01:36:41PM +0000, Conor Dooley wrote: > On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote: > > On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote: > > > > The above two methods can fix the problem. Here are my test results. > > > The VisionFive board can boot up successfully if and only if all above > > > two applied. > > > The VisionFive 2 board can boot up successfully if I merge Linus's new > > > changes. > > > > Tested also on my side. Hope this can be helpfull. > > > > > Hope your fix will be merged in rc2. Thank you for your reply. > > > > Fully agree. > > If you only have a VisionFive 2, it shouldn't matter to you, as you > don't need to fix up any SiFive errata (at the moment at least). > Linus' fix is already in his tree, so should be in -rc2! > The fix for the VisionFive was applied to Palmer's RISC-V fixes tree > last night: > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b > > Thanks, > Conor. Hi Conor, Thanks for the info. Playing with this series I got the following error: [ 6.278182] BUG: spinlock bad magic on CPU#0, udevd/136 [ 6.283414] lock: 0xffffffd84135e6c0, .magic: ffffffff, .owner: <none>/-1, .owner_cpu: -1 [ 6.291677] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14 [ 6.299502] Hardware name: StarFive VisionFive 2 v1.3B (DT) [ 6.305069] Call Trace: [ 6.307517] [<ffffffff80005530>] dump_backtrace+0x1c/0x24 [ 6.312921] [<ffffffff80844b4e>] show_stack+0x2c/0x38 [ 6.317976] [<ffffffff8085032c>] dump_stack_lvl+0x3c/0x54 [ 6.323377] [<ffffffff80850358>] dump_stack+0x14/0x1c [ 6.328429] [<ffffffff80845668>] spin_dump+0x64/0x70 [ 6.333394] [<ffffffff80058f26>] do_raw_spin_lock+0xb4/0xf2 [ 6.338970] [<ffffffff80857d04>] _raw_spin_lock+0x1a/0x22 [ 6.344370] [<ffffffff8008153c>] add_timer_on+0x8a/0x132 [ 6.349684] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278 [ 6.356037] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8 [ 6.361697] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8 [ 6.366752] [<ffffffff801a1986>] ksys_read+0x5e/0xc8 [ 6.371710] [<ffffffff801a19fe>] sys_read+0xe/0x16 [ 6.376503] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2 [ 6.381905] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000007 [ 6.390683] Oops [#1] [ 6.392956] Modules linked in: [ 6.396011] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14 [ 6.403835] Hardware name: StarFive VisionFive 2 v1.3B (DT) [ 6.409401] epc : enqueue_timer+0x1a/0x90 [ 6.413414] ra : add_timer_on+0xe2/0x132 [ 6.417425] epc : ffffffff80080c60 ra : ffffffff80081594 sp : ffffffc8044dbc60 [ 6.424640] gp : ffffffff814ffe50 tp : ffffffd8c171ad00 t0 : 6666666666663c5b [ 6.431855] t1 : 000000000000005b t2 : 666666666666663c s0 : ffffffc8044dbcc0 [ 6.439070] s1 : ffffffc8044dbd08 a0 : ffffffd84135e6c0 a1 : ffffffc8044dbd08 [ 6.446284] a2 : ffffffffffffffff a3 : 000000003e000000 a4 : 000000000000023e [ 6.453498] a5 : 000000000000023e a6 : ffffffd84135f930 a7 : 0000000000000038 [ 6.460712] s2 : ffffffd84135e6c0 s3 : 0000000000000040 s4 : ffffffff81501080 [ 6.467926] s5 : ffffffd84135e6c0 s6 : ffffffff815011b8 s7 : ffffffffffffffff [ 6.475141] s8 : ffffffff81502820 s9 : 0000000000000040 s10: 0000002ab0a49320 [ 6.482355] s11: 0000000000000001 t3 : ffffffff81512e97 t4 : ffffffff81512e97 [ 6.489569] t5 : ffffffff81512e98 t6 : ffffffc8044db948 [ 6.494875] status: 0000000200000100 badaddr: 0000000000000007 cause: 000000000000000f [ 6.502783] [<ffffffff80080c60>] enqueue_timer+0x1a/0x90 [ 6.508095] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278 [ 6.514448] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8 [ 6.520107] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8 [ 6.525160] [<ffffffff801a1986>] ksys_read+0x5e/0xc8 [ 6.530126] [<ffffffff801a19fe>] sys_read+0xe/0x16 [ 6.534918] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2 [ 6.540322] Code: 87b2 0813 0805 1613 0037 9832 3603 0008 e190 c211 (e60c) 5613 [ 6.547711] ---[ end trace 0000000000000000 ]--- [ 6.552325] note: udevd[136] exited with irqs disabled [ 6.557531] note: udevd[136] exited with preempt_count 2 I'm working on top of Linux version 6.3.0-rc1-g92569901a7f. Did you already see this crash? Let me know. Thanks, Tommaso
On Thu, Mar 09, 2023 at 05:49:48PM +0100, Tommaso Merciai wrote: > On Wed, Mar 08, 2023 at 01:36:41PM +0000, Conor Dooley wrote: > > On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote: > > > On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote: > > > > > > The above two methods can fix the problem. Here are my test results. > > > > The VisionFive board can boot up successfully if and only if all above > > > > two applied. > > > > The VisionFive 2 board can boot up successfully if I merge Linus's new > > > > changes. > > > > > > Tested also on my side. Hope this can be helpfull. > > > > > > > Hope your fix will be merged in rc2. Thank you for your reply. > > > > > > Fully agree. > > > > If you only have a VisionFive 2, it shouldn't matter to you, as you > > don't need to fix up any SiFive errata (at the moment at least). > > Linus' fix is already in his tree, so should be in -rc2! > > The fix for the VisionFive was applied to Palmer's RISC-V fixes tree > > last night: > > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b > > > > Thanks, > > Conor. > > > Hi Conor, > Thanks for the info. > Playing with this series I got the following error: > > [ 6.278182] BUG: spinlock bad magic on CPU#0, udevd/136 > [ 6.283414] lock: 0xffffffd84135e6c0, .magic: ffffffff, .owner: <none>/-1, .owner_cpu: -1 > [ 6.291677] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14 > [ 6.299502] Hardware name: StarFive VisionFive 2 v1.3B (DT) > [ 6.305069] Call Trace: > [ 6.307517] [<ffffffff80005530>] dump_backtrace+0x1c/0x24 > [ 6.312921] [<ffffffff80844b4e>] show_stack+0x2c/0x38 > [ 6.317976] [<ffffffff8085032c>] dump_stack_lvl+0x3c/0x54 > [ 6.323377] [<ffffffff80850358>] dump_stack+0x14/0x1c > [ 6.328429] [<ffffffff80845668>] spin_dump+0x64/0x70 > [ 6.333394] [<ffffffff80058f26>] do_raw_spin_lock+0xb4/0xf2 > [ 6.338970] [<ffffffff80857d04>] _raw_spin_lock+0x1a/0x22 > [ 6.344370] [<ffffffff8008153c>] add_timer_on+0x8a/0x132 > [ 6.349684] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278 > [ 6.356037] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8 > [ 6.361697] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8 > [ 6.366752] [<ffffffff801a1986>] ksys_read+0x5e/0xc8 > [ 6.371710] [<ffffffff801a19fe>] sys_read+0xe/0x16 > [ 6.376503] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2 > [ 6.381905] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000007 > [ 6.390683] Oops [#1] > [ 6.392956] Modules linked in: > [ 6.396011] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14 > [ 6.403835] Hardware name: StarFive VisionFive 2 v1.3B (DT) > [ 6.409401] epc : enqueue_timer+0x1a/0x90 > [ 6.413414] ra : add_timer_on+0xe2/0x132 > [ 6.417425] epc : ffffffff80080c60 ra : ffffffff80081594 sp : ffffffc8044dbc60 > [ 6.424640] gp : ffffffff814ffe50 tp : ffffffd8c171ad00 t0 : 6666666666663c5b > [ 6.431855] t1 : 000000000000005b t2 : 666666666666663c s0 : ffffffc8044dbcc0 > [ 6.439070] s1 : ffffffc8044dbd08 a0 : ffffffd84135e6c0 a1 : ffffffc8044dbd08 > [ 6.446284] a2 : ffffffffffffffff a3 : 000000003e000000 a4 : 000000000000023e > [ 6.453498] a5 : 000000000000023e a6 : ffffffd84135f930 a7 : 0000000000000038 > [ 6.460712] s2 : ffffffd84135e6c0 s3 : 0000000000000040 s4 : ffffffff81501080 > [ 6.467926] s5 : ffffffd84135e6c0 s6 : ffffffff815011b8 s7 : ffffffffffffffff > [ 6.475141] s8 : ffffffff81502820 s9 : 0000000000000040 s10: 0000002ab0a49320 > [ 6.482355] s11: 0000000000000001 t3 : ffffffff81512e97 t4 : ffffffff81512e97 > [ 6.489569] t5 : ffffffff81512e98 t6 : ffffffc8044db948 > [ 6.494875] status: 0000000200000100 badaddr: 0000000000000007 cause: 000000000000000f > [ 6.502783] [<ffffffff80080c60>] enqueue_timer+0x1a/0x90 > [ 6.508095] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278 > [ 6.514448] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8 > [ 6.520107] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8 > [ 6.525160] [<ffffffff801a1986>] ksys_read+0x5e/0xc8 > [ 6.530126] [<ffffffff801a19fe>] sys_read+0xe/0x16 > [ 6.534918] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2 > [ 6.540322] Code: 87b2 0813 0805 1613 0037 9832 3603 0008 e190 c211 (e60c) 5613 > [ 6.547711] ---[ end trace 0000000000000000 ]--- > [ 6.552325] note: udevd[136] exited with irqs disabled > [ 6.557531] note: udevd[136] exited with preempt_count 2 > > > I'm working on top of Linux version 6.3.0-rc1-g92569901a7f. Unfortunately, this g<sha> bit doesn't mean anything outside of your repo so it's hard to infer anything from that. This looks exactly like a bug is in v6.3-rc1, but Linus fixed in like the second commit *after* -rc1. What branch/commit/tag did you apply the series on top of? Cheers, Conor.
On Thu, Mar 09, 2023 at 05:52:49PM +0000, Conor Dooley wrote: > On Thu, Mar 09, 2023 at 05:49:48PM +0100, Tommaso Merciai wrote: > > On Wed, Mar 08, 2023 at 01:36:41PM +0000, Conor Dooley wrote: > > > On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote: > > > > On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote: > > > > > > > > The above two methods can fix the problem. Here are my test results. > > > > > The VisionFive board can boot up successfully if and only if all above > > > > > two applied. > > > > > The VisionFive 2 board can boot up successfully if I merge Linus's new > > > > > changes. > > > > > > > > Tested also on my side. Hope this can be helpfull. > > > > > > > > > Hope your fix will be merged in rc2. Thank you for your reply. > > > > > > > > Fully agree. > > > > > > If you only have a VisionFive 2, it shouldn't matter to you, as you > > > don't need to fix up any SiFive errata (at the moment at least). > > > Linus' fix is already in his tree, so should be in -rc2! > > > The fix for the VisionFive was applied to Palmer's RISC-V fixes tree > > > last night: > > > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b > > > > > > Thanks, > > > Conor. > > > > > > Hi Conor, > > Thanks for the info. > > Playing with this series I got the following error: > > > > [ 6.278182] BUG: spinlock bad magic on CPU#0, udevd/136 > > [ 6.283414] lock: 0xffffffd84135e6c0, .magic: ffffffff, .owner: <none>/-1, .owner_cpu: -1 > > [ 6.291677] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14 > > [ 6.299502] Hardware name: StarFive VisionFive 2 v1.3B (DT) > > [ 6.305069] Call Trace: > > [ 6.307517] [<ffffffff80005530>] dump_backtrace+0x1c/0x24 > > [ 6.312921] [<ffffffff80844b4e>] show_stack+0x2c/0x38 > > [ 6.317976] [<ffffffff8085032c>] dump_stack_lvl+0x3c/0x54 > > [ 6.323377] [<ffffffff80850358>] dump_stack+0x14/0x1c > > [ 6.328429] [<ffffffff80845668>] spin_dump+0x64/0x70 > > [ 6.333394] [<ffffffff80058f26>] do_raw_spin_lock+0xb4/0xf2 > > [ 6.338970] [<ffffffff80857d04>] _raw_spin_lock+0x1a/0x22 > > [ 6.344370] [<ffffffff8008153c>] add_timer_on+0x8a/0x132 > > [ 6.349684] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278 > > [ 6.356037] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8 > > [ 6.361697] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8 > > [ 6.366752] [<ffffffff801a1986>] ksys_read+0x5e/0xc8 > > [ 6.371710] [<ffffffff801a19fe>] sys_read+0xe/0x16 > > [ 6.376503] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2 > > [ 6.381905] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000007 > > [ 6.390683] Oops [#1] > > [ 6.392956] Modules linked in: > > [ 6.396011] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14 > > [ 6.403835] Hardware name: StarFive VisionFive 2 v1.3B (DT) > > [ 6.409401] epc : enqueue_timer+0x1a/0x90 > > [ 6.413414] ra : add_timer_on+0xe2/0x132 > > [ 6.417425] epc : ffffffff80080c60 ra : ffffffff80081594 sp : ffffffc8044dbc60 > > [ 6.424640] gp : ffffffff814ffe50 tp : ffffffd8c171ad00 t0 : 6666666666663c5b > > [ 6.431855] t1 : 000000000000005b t2 : 666666666666663c s0 : ffffffc8044dbcc0 > > [ 6.439070] s1 : ffffffc8044dbd08 a0 : ffffffd84135e6c0 a1 : ffffffc8044dbd08 > > [ 6.446284] a2 : ffffffffffffffff a3 : 000000003e000000 a4 : 000000000000023e > > [ 6.453498] a5 : 000000000000023e a6 : ffffffd84135f930 a7 : 0000000000000038 > > [ 6.460712] s2 : ffffffd84135e6c0 s3 : 0000000000000040 s4 : ffffffff81501080 > > [ 6.467926] s5 : ffffffd84135e6c0 s6 : ffffffff815011b8 s7 : ffffffffffffffff > > [ 6.475141] s8 : ffffffff81502820 s9 : 0000000000000040 s10: 0000002ab0a49320 > > [ 6.482355] s11: 0000000000000001 t3 : ffffffff81512e97 t4 : ffffffff81512e97 > > [ 6.489569] t5 : ffffffff81512e98 t6 : ffffffc8044db948 > > [ 6.494875] status: 0000000200000100 badaddr: 0000000000000007 cause: 000000000000000f > > [ 6.502783] [<ffffffff80080c60>] enqueue_timer+0x1a/0x90 > > [ 6.508095] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278 > > [ 6.514448] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8 > > [ 6.520107] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8 > > [ 6.525160] [<ffffffff801a1986>] ksys_read+0x5e/0xc8 > > [ 6.530126] [<ffffffff801a19fe>] sys_read+0xe/0x16 > > [ 6.534918] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2 > > [ 6.540322] Code: 87b2 0813 0805 1613 0037 9832 3603 0008 e190 c211 (e60c) 5613 > > [ 6.547711] ---[ end trace 0000000000000000 ]--- > > [ 6.552325] note: udevd[136] exited with irqs disabled > > [ 6.557531] note: udevd[136] exited with preempt_count 2 > > > > > > I'm working on top of Linux version 6.3.0-rc1-g92569901a7f. Hi Conor, > > Unfortunately, this g<sha> bit doesn't mean anything outside of your > repo so it's hard to infer anything from that. > This looks exactly like a bug is in v6.3-rc1, but Linus fixed in like > the second commit *after* -rc1. Thanks for the tips. I rebase my working branch on top of: 6a98c9cae232 (origin/master, origin/HEAD) Merge tag 'fs_for_v6.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs https://github.com/Scott31393/linux/tree/tm/master_visionv2_v1.3b_vf2-6.2-gmac I'm able to boot the board using nfs ;) (without issue) [ 0.000000] Linux version 6.3.0-rc1-gcf4a201af313 (tom@tom-HP-ZBook-Fury-15-G7-Mobile-Workstation) (riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot VF2_v2.10.4) 10.3.0, GNU ld (GNU Binutils) 2.36.1) #16 SM P Thu Mar 9 19:31:50 CET 2023 [ 0.000000] OF: fdt: Ignoring memory range 0x40000000 - 0x40200000 [ 0.000000] Machine model: StarFive VisionFive 2 v1.3B [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') [ 0.000000] printk: bootconsole [sbi0] enabled [ 0.000000] efi: UEFI not found. [ 0.000000] Zone ranges: [ 0.000000] DMA32 [mem 0x0000000040200000-0x00000000ffffffff] [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Movable zone start for each node > > What branch/commit/tag did you apply the series on top of? Thanks again, Tommaso > > Cheers, > Conor.
On Thu, Mar 09, 2023 at 07:58:21PM +0100, Tommaso Merciai wrote: > I'm able to boot the board using nfs ;) > (without issue) Sweet, glad you got it working. If you'd like to provide a Tested-by: for the series that'd be wonderful too :) No pressure haha
Hello Conor, On Thu, Mar 09, 2023 at 07:03:47PM +0000, Conor Dooley wrote: > On Thu, Mar 09, 2023 at 07:58:21PM +0100, Tommaso Merciai wrote: > > > I'm able to boot the board using nfs ;) > > (without issue) > > Sweet, glad you got it working. If you'd like to provide a Tested-by: > for the series that'd be wonderful too :) No pressure haha > Yes ofc I provide my Tested-by ;) I collect some other series like gmac integration. I need to clarify. btw below my tag on this series :) Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Thanks & Regards, Tommaso
This patch series adds basic clock, reset & DT support for StarFive JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl dt-bindings. Patch 19 depends on series [2] which provides dt-bindings of VisionFive 2 board and JH7110 SoC. You can simply review or test the patches at the link [3]. [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/ [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/ [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal Changes since v3: - Suggested by Conor, Merged clock & reset series and DT series together so that they could go via the same tree as the dt-binding headers are required by both driver & devicetree. - Rebased on tag v6.2. [Clock & reset] Patch 2: - Split patch 2 into two. One for renaming file and one for renaming variables. (by Conor) Patch 4: - Split patch 4 into two. One for code movement and one for extraction. (by Conor) Patch 5 & 9 & 10 & 11: - Fixed the issues reported by kernel test robot. Patch 9: - Set (&priv->base) as driver data instead of (priv->base). - Set the frequency of clock PLL0 as 1000MHz for Synchronizing with the lastest u-boot setting from StarFive. (by Emil) - Used devm_kzalloc() instead of kzalloc() when registering aux device. Patch 10: - Set (&priv->base) as driver data instead of (priv->base). Patch 11: - Used (*base) to get the register base address instead of (base). [Device tree] - Dropped patch 1, 4, 5 because they were accepted. - Added a new patch to add SiFive S7 compatible. (by Conor) - Added a new patch to add JH7110 pin function definitions. Patch 6: - Changed the label "S76_0" to "S7_0" and used compatible "sifive,s7" for core 0. - Updated ISA of each cores. (by Conor) - Made the node names generic. (by Krzysztof) - Added clock-output-names for all external clocks. - Added i2c0~6 nodes. - Changed the node name "gpio" to "pinctrl". Changed the label "gpio" and "gpioa" to "sysgpio" and "aongpio". (by Conor) Patch 7: - Separated the long lines into more lines in Makefile. (by Conor) - Renamed jh7110-starfive-visionfive-2-va.dts and jh7110-starfive-visionfive-2-vb.dts to jh7110-starfive-visionfive-2-v1.2a.dts and jh7110-starfive-visionfive-2-v1.3b.dts. Changed the model and compatible to match v1.2A and v1.3B which are printed on the silkscreen of VisionFive 2 board. (by Emil) - Configured pins for i2c0/2/5/6 and enabled them. clock & reset v3: https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/ DT v3: https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/ Changes since v2: [Clock & reset] - Rebased on tag v6.1. - Added "JH71X0" to the StarFive driver headers in MAINTAINERS. - Removed Co-developed-by tag of Hal in patch 1 and patch 4. - Changed the commit author from Hal to Emil in patch 2 and patch 5. Removed Co-developed-by tag of Emil in patch 2 and patch 5. (by Emil) - Improved the coding style of patch 11, 12 and 13. - Dropped patch 14. (by Emil) Patch 4: - Passed the "owner" member of reset_controller_dev structure directly in reset_starfive_jh7100_register(). (by Emil) - Added MAINTAINERS changes. Patch 7: - Split patch 7 into sys part and aon part. Merged them into patch 9 and patch 10 respectively. (by Krzysztof) - Renamed include/dt-bindings/clock/starfive-jh7110.h to include/dt-bindings/clock/starfive,jh7110-crg.h. (by Krzysztof) - Synchronized the definitions with the latest changes from Emil. Patch 8: - Split patch 8 into sys part and aon part. Merged them into patch 9 and patch 10 respectively. (by Krzysztof) - Renamed include/dt-bindings/reset/starfive-jh7110.h to include/dt-bindings/reset/starfive,jh7110-crg.h. (by Krzysztof) - Fixed the date of Copyright. (by Emil) - Dropped weird indentations. (by Krzysztof) - Synchronized the definitions with the latest changes from Emil. Patch 9: - Improved the description of clocks. (by Emil and Krzysztof) - Added MAINTAINERS changes. Patch 10: - Improved the description of clocks. (by Emil and Krzysztof) - Changed the clock-name "clk_rtc" to "rtc_osc" and "apb_bus_func" to "apb_bus". Patch 11: - Removed the flags of trace/debug clocks and set the flags of core clocks as CLK_IS_CRITICAL. (by Emil) - Deleted the extra 1-1 clocks and synchronized the clock tree with the latest changes from Emil. (by Emil) - Selected RESET_STARFIVE_JH7110 in Kconfig option CLK_STARFIVE_JH7110_SYS. Patch 12: - Changed the macro JH7110_AONCLK_RTC to JH7110_AONCLK_RTC_OSC and JH7110_AONCLK_APB_BUS_FUNC to JH7110_AONCLK_APB_BUS. - Synchronized the clock tree with the latest changes from Emil. - Set the MODULE_LICENSE as "GPL" according to commit bf7fbeeae6db. Patch 13: - Removed the "asserted" member in reset_info structure and always pass NULL when calling reset_starfive_jh71x0_register(). (by Emil) [Device tree] - Rebased on tag v6.1. - Dropped patch 8 because it was merged. Patch 1: - Made the links into "Link:" tags. (by Conor) - Corrected the board name to "VisionFive 2" instead of "VisionFive V2" and added compatibles for version A and version B of VisionFive 2. (by Emil) Patch 4: - Used "sifive,ccache0" compatible string to match. (by Conor) Patch 5: - Dropped "select SIFIVE_CCACHE" in config SOC_STARFIVE. (by Conor) - Dropped "starfive,jh7110-ccache" compatible in drivers/soc/sifive/sifive_ccache.c. Patch 6: - Removed all "clock-frequency = <0>". (by Conor) - Sorted the nodes after their addresses. (by Emil) - Renamed "clk_rtc" to "rtc_osc". - Added "sifive,ccache0" compatible in the cache-controller node. - Renamed "JH7110_SYSCLK_APB_BUS_FUNC" to "JH7110_SYSCLK_APB_BUS" and renamed "apb_bus_func" to "apb_bus". Renamed "JH7110_SYSCLK_IOMUX" to "JH7110_SYSCLK_IOMUX_APB". Renamed "JH7110_SYSRST_IOMUX" to "JH7110_SYSRST_IOMUX_APB". Renamed "JH7110_AONRST_AON_IOMUX" to "JH7110_AONRST_IOMUX". - Removed "reg-names" in gpio nodes. Patch 7: - Corrected the board name to "VisionFive 2" instead of "VisionFive V2". - Renamed jh7110-starfive-visionfive-v2.dts to jh7110-starfive-visionfive-2.dtsi. - Added dts for VisionFive 2 version A and version B boards. - In the chosen node, deleted "linux,initrd-start" and "linux,initrd-end" and changed the value of "stdout-path" to "serial0:115200n8". - Changed the bias of uart0 "rx-pins" to "bias-disable; /* external pull-up */". - Renamed "clk_rtc" to "rtc_osc". - Moved the gpio node behind the uart0 node. clock & reset v2: https://lore.kernel.org/all/20221118010627.70576-1-hal.feng@starfivetech.com/ DT v2: https://lore.kernel.org/all/20221118011714.70877-1-hal.feng@starfivetech.com/ Changes since v1: [Clock & reset] - Rebased on tag v6.1-rc5. - Rewrote the clock and reset drivers using auxiliary bus framework, so patch 8, 9, 15 were dropped and all patches changed a lot. (by Stephen) - Split Patch 14 into two patches. One is for factoring out the common JH71X0 code, the another one is for renaming. (by Stephen) - Created a subdirectory for StarFive reset drivers. - Factored out common JH71X0 reset code. - Renamed the common clock and reset code from "*starfive*" or "*STARFIVE*" to "*jh71x0*" or "*JH71X0*". - Combined JH7110 system and always-on clock DT binding headers in one file named "include/dt-bindings/clock/starfive-jh7110.h". - Renamed clock definitions "JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK" and "JH7110_SYSCLK_U2_PCLK_MUX_PCLK" to "JH7110_SYSCLK_PCLK2_MUX_FUNC" and "JH7110_SYSCLK_PCLK2_MUX". - Rewrote the DT bindings of clock and reset for using auxiliary bus. - Registered an auxiliary device for reset controller in clock drivers. - Changed clock names "CODAJ*" and "WAVE*" to "codaj*" and "wave*". Changed clock names "u2_pclk_mux_func_pclk" and "u2_pclk_mux_pclk" to "pclk2_mux_func" and "pclk2_mux". - Changed the flags of clock apb0 and noc_bus_isp_axi to CLK_IS_CRITICAL as suggested by StarFive SDK group. - Registered clock gmac0_gtxc as a gate clock instead of a div clock as suggested by StarFive SDK group. - Changed the frequency of clock pll2_out to 1188MHz as suggested by StarFive SDK group. - Fixed the bug that the clock JH7110_AONCLK_GMAC0_GTXCLK was not handled in JH7110 always-on clock driver. - Registered the reset driver as an auxiliary driver. - Reworded the commit messages. [Device tree] - Rebased on tag v6.1-rc5. - Added blank line in patch 1. (by Krzysztof) - Rebased patch 4 and 6 on the newest code. (by Conor) - Dropped patch 5. (by Conor) - Removed the quirk of JH7100 in patch 6, considering this patch series should only add support for JH7110. - For patch 27, added Co-developed-by tag for Jianlong and me. Renamed cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts. Rewrote clock-controller nodes and deleted reset-controller nodes for using auxiliary bus. Rewrote gpio nodes following generic pinctrl bindings. Removed the redundant second reset entry of uart nodes. - For patch 28, added Co-developed-by tag for Jianlong and me. Added a chosen node. Removed reserved-memory node. Added fixed frequency clock nodes for overriding the "clock-frequency" properties. Rewrote the gpio nodes following generic pinctrl bindings. - Dropped patch 30. (by Conor) - Reworded the commit messages. v1: https://lore.kernel.org/all/20220929143225.17907-1-hal.feng@linux.starfivetech.com/ Emil Renner Berthing (16): clk: starfive: Factor out common JH7100 and JH7110 code clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h clk: starfive: Rename "jh7100" to "jh71x0" for the common code reset: Create subdirectory for StarFive drivers reset: starfive: Factor out common JH71X0 reset code reset: starfive: Extract the common JH71X0 reset code reset: starfive: Rename "jh7100" to "jh71x0" for the common code reset: starfive: jh71x0: Use 32bit I/O on 32bit registers dt-bindings: clock: Add StarFive JH7110 system clock and reset generator dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator clk: starfive: Add StarFive JH7110 system clock driver clk: starfive: Add StarFive JH7110 always-on clock driver dt-bindings: timer: Add StarFive JH7110 clint dt-bindings: interrupt-controller: Add StarFive JH7110 plic riscv: dts: starfive: Add initial StarFive JH7110 device tree riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng (2): reset: starfive: Add StarFive JH7110 reset driver dt-bindings: riscv: Add SiFive S7 compatible Jianlong Huang (1): riscv: dts: starfive: Add StarFive JH7110 pin function definitions .../clock/starfive,jh7110-aoncrg.yaml | 76 ++ .../clock/starfive,jh7110-syscrg.yaml | 80 ++ .../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/cpus.yaml | 1 + .../bindings/timer/sifive,clint.yaml | 1 + MAINTAINERS | 16 +- arch/riscv/boot/dts/starfive/Makefile | 6 +- arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++++ .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 + .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 + .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 507 +++++++++++++ drivers/clk/starfive/Kconfig | 27 + drivers/clk/starfive/Makefile | 6 +- .../clk/starfive/clk-starfive-jh7100-audio.c | 74 +- drivers/clk/starfive/clk-starfive-jh7100.c | 713 +++++------------- drivers/clk/starfive/clk-starfive-jh7100.h | 112 --- .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++ .../clk/starfive/clk-starfive-jh7110-sys.c | 448 +++++++++++ drivers/clk/starfive/clk-starfive-jh71x0.c | 383 ++++++++++ drivers/clk/starfive/clk-starfive-jh71x0.h | 122 +++ drivers/reset/Kconfig | 8 +- drivers/reset/Makefile | 2 +- drivers/reset/reset-starfive-jh7100.c | 173 ----- drivers/reset/starfive/Kconfig | 20 + drivers/reset/starfive/Makefile | 5 + .../reset/starfive/reset-starfive-jh7100.c | 74 ++ .../reset/starfive/reset-starfive-jh7110.c | 64 ++ .../reset/starfive/reset-starfive-jh71x0.c | 131 ++++ .../reset/starfive/reset-starfive-jh71x0.h | 20 + .../dt-bindings/clock/starfive,jh7110-crg.h | 225 ++++++ .../dt-bindings/reset/starfive,jh7110-crg.h | 154 ++++ 32 files changed, 3296 insertions(+), 858 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h delete mode 100644 drivers/reset/reset-starfive-jh7100.c create mode 100644 drivers/reset/starfive/Kconfig create mode 100644 drivers/reset/starfive/Makefile create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.c create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h base-commit: c9c3395d5e3dcc6daee66c6908354d47bf98cb0c