| Message ID | 20230930123937.1551-5-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add Milk-V Duo board support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
Hi, Jisheng You add the clint dt-bindings of CV1800B clint, but I don't see the clint node in this dt. The SBI needs this clint node to provide timer for linux. AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader may load the linux dt and pass it to the SBI. I think it is better to add the clint node. In addition, please separate the peripheral node to a different file, which can be reused by both the CV1800 series and CV1810 series. Thanks, Inochi > >Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > >Signed-off-by: Jisheng Zhang <jszhang@kernel.org> >--- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ > 1 file changed, 117 insertions(+) > create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi > >diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >new file mode 100644 >index 000000000000..8829bebaa017 >--- /dev/null >+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >@@ -0,0 +1,117 @@ >+// SPDX-License-Identifier: (GPL-2.0 OR MIT) >+/* >+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> >+ */ >+ >+#include <dt-bindings/interrupt-controller/irq.h> >+ >+/ { >+ compatible = "sophgo,cv1800b"; >+ #address-cells = <1>; >+ #size-cells = <1>; >+ >+ cpus: cpus { >+ #address-cells = <1>; >+ #size-cells = <0>; >+ timebase-frequency = <25000000>; >+ >+ cpu0: cpu@0 { >+ compatible = "thead,c906", "riscv"; >+ device_type = "cpu"; >+ reg = <0>; >+ d-cache-block-size = <64>; >+ d-cache-sets = <512>; >+ d-cache-size = <65536>; >+ i-cache-block-size = <64>; >+ i-cache-sets = <128>; >+ i-cache-size = <32768>; >+ mmu-type = "riscv,sv39"; >+ riscv,isa = "rv64imafdc"; >+ riscv,isa-base = "rv64i"; >+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", >+ "zifencei", "zihpm"; >+ >+ cpu0_intc: interrupt-controller { >+ compatible = "riscv,cpu-intc"; >+ interrupt-controller; >+ #address-cells = <0>; >+ #interrupt-cells = <1>; >+ }; >+ }; >+ }; >+ >+ osc: oscillator { >+ compatible = "fixed-clock"; >+ clock-output-names = "osc_25m"; >+ #clock-cells = <0>; >+ }; >+ >+ soc { >+ compatible = "simple-bus"; >+ interrupt-parent = <&plic>; >+ #address-cells = <1>; >+ #size-cells = <1>; >+ dma-noncoherent; >+ ranges; >+ >+ uart0: serial@04140000 { >+ compatible = "snps,dw-apb-uart"; >+ reg = <0x04140000 0x100>; >+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; >+ clocks = <&osc>; >+ reg-shift = <2>; >+ reg-io-width = <4>; >+ status = "disabled"; >+ }; >+ >+ uart1: serial@04150000 { >+ compatible = "snps,dw-apb-uart"; >+ reg = <0x04150000 0x100>; >+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; >+ clocks = <&osc>; >+ reg-shift = <2>; >+ reg-io-width = <4>; >+ status = "disabled"; >+ }; >+ >+ uart2: serial@04160000 { >+ compatible = "snps,dw-apb-uart"; >+ reg = <0x04160000 0x100>; >+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; >+ clocks = <&osc>; >+ reg-shift = <2>; >+ reg-io-width = <4>; >+ status = "disabled"; >+ }; >+ >+ uart3: serial@04170000 { >+ compatible = "snps,dw-apb-uart"; >+ reg = <0x04170000 0x100>; >+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; >+ clocks = <&osc>; >+ reg-shift = <2>; >+ reg-io-width = <4>; >+ status = "disabled"; >+ }; >+ >+ uart4: serial@041c0000 { >+ compatible = "snps,dw-apb-uart"; >+ reg = <0x041c0000 0x100>; >+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; >+ clocks = <&osc>; >+ reg-shift = <2>; >+ reg-io-width = <4>; >+ status = "disabled"; >+ }; >+ >+ plic: interrupt-controller@70000000 { >+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; >+ reg = <0x70000000 0x4000000>; >+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; >+ interrupt-controller; >+ #address-cells = <0>; >+ #interrupt-cells = <2>; >+ riscv,ndev = <101>; >+ }; >+ }; >+}; >-- >2.40.1 > >
On Sun, Oct 01, 2023 at 06:34:21AM +0800, Inochi Amaoto wrote: > Hi, Jisheng > >Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > > You add the clint dt-bindings of CV1800B clint, but I don't see the clint > node in this dt. The SBI needs this clint node to provide timer for linux. > AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader > may load the linux dt and pass it to the SBI. I think it is better to add > the clint node. > In addition, please separate the peripheral node to a different file, which > can be reused by both the CV1800 series and CV1810 series. How do these SoCs differ? Documentation seems rather lacking, but I was able to find something on github that suggests there is also a cv180zb. The difference between the three seems to, from a quick look, be their video encoding capabilities. Is that correct? Cheers, Conor. > > > >Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > >--- > > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ > > 1 file changed, 117 insertions(+) > > create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > > >diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > >new file mode 100644 > >index 000000000000..8829bebaa017 > >--- /dev/null > >+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > >@@ -0,0 +1,117 @@ > >+// SPDX-License-Identifier: (GPL-2.0 OR MIT) > >+/* > >+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > >+ */ > >+ > >+#include <dt-bindings/interrupt-controller/irq.h> > >+ > >+/ { > >+ compatible = "sophgo,cv1800b"; > >+ #address-cells = <1>; > >+ #size-cells = <1>; > >+ > >+ cpus: cpus { > >+ #address-cells = <1>; > >+ #size-cells = <0>; > >+ timebase-frequency = <25000000>; > >+ > >+ cpu0: cpu@0 { > >+ compatible = "thead,c906", "riscv"; > >+ device_type = "cpu"; > >+ reg = <0>; > >+ d-cache-block-size = <64>; > >+ d-cache-sets = <512>; > >+ d-cache-size = <65536>; > >+ i-cache-block-size = <64>; > >+ i-cache-sets = <128>; > >+ i-cache-size = <32768>; > >+ mmu-type = "riscv,sv39"; > >+ riscv,isa = "rv64imafdc"; > >+ riscv,isa-base = "rv64i"; > >+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > >+ "zifencei", "zihpm"; > >+ > >+ cpu0_intc: interrupt-controller { > >+ compatible = "riscv,cpu-intc"; > >+ interrupt-controller; > >+ #address-cells = <0>; > >+ #interrupt-cells = <1>; > >+ }; > >+ }; > >+ }; > >+ > >+ osc: oscillator { > >+ compatible = "fixed-clock"; > >+ clock-output-names = "osc_25m"; > >+ #clock-cells = <0>; > >+ }; > >+ > >+ soc { > >+ compatible = "simple-bus"; > >+ interrupt-parent = <&plic>; > >+ #address-cells = <1>; > >+ #size-cells = <1>; > >+ dma-noncoherent; > >+ ranges; > >+ > >+ uart0: serial@04140000 { > >+ compatible = "snps,dw-apb-uart"; > >+ reg = <0x04140000 0x100>; > >+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > >+ clocks = <&osc>; > >+ reg-shift = <2>; > >+ reg-io-width = <4>; > >+ status = "disabled"; > >+ }; > >+ > >+ uart1: serial@04150000 { > >+ compatible = "snps,dw-apb-uart"; > >+ reg = <0x04150000 0x100>; > >+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > >+ clocks = <&osc>; > >+ reg-shift = <2>; > >+ reg-io-width = <4>; > >+ status = "disabled"; > >+ }; > >+ > >+ uart2: serial@04160000 { > >+ compatible = "snps,dw-apb-uart"; > >+ reg = <0x04160000 0x100>; > >+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > >+ clocks = <&osc>; > >+ reg-shift = <2>; > >+ reg-io-width = <4>; > >+ status = "disabled"; > >+ }; > >+ > >+ uart3: serial@04170000 { > >+ compatible = "snps,dw-apb-uart"; > >+ reg = <0x04170000 0x100>; > >+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > >+ clocks = <&osc>; > >+ reg-shift = <2>; > >+ reg-io-width = <4>; > >+ status = "disabled"; > >+ }; > >+ > >+ uart4: serial@041c0000 { > >+ compatible = "snps,dw-apb-uart"; > >+ reg = <0x041c0000 0x100>; > >+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; > >+ clocks = <&osc>; > >+ reg-shift = <2>; > >+ reg-io-width = <4>; > >+ status = "disabled"; > >+ }; > >+ > >+ plic: interrupt-controller@70000000 { > >+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > >+ reg = <0x70000000 0x4000000>; > >+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > >+ interrupt-controller; > >+ #address-cells = <0>; > >+ #interrupt-cells = <2>; > >+ riscv,ndev = <101>; > >+ }; > >+ }; > >+}; > >-- > >2.40.1 > > > >
>On Sun, Oct 01, 2023 at 06:34:21AM +0800, Inochi Amaoto wrote: >> Hi, Jisheng > >>> Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > >> >> You add the clint dt-bindings of CV1800B clint, but I don't see the clint >> node in this dt. The SBI needs this clint node to provide timer for linux. >> AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader >> may load the linux dt and pass it to the SBI. I think it is better to add >> the clint node. > >> In addition, please separate the peripheral node to a different file, which >> can be reused by both the CV1800 series and CV1810 series. > >How do these SoCs differ? AFAIK, the most peripheral of CV1800 and CV1810 are the same. there are only a few difference between CV1800 and CV1810: 1. CV1810 have mmc interrupt, but CV1800 have none 2. CV1810 have more RAM and a more powerful TPU. 3. Some models of CV1810 support I2S. Also is some you have already mentioned, the video capabilities (including encoding, output steam number, input steam number) are different. The only board with a CV1800 soc is Huashan Pi (CV1812H). >Documentation seems rather lacking, but I was able to find something on >github that suggests there is also a cv180zb. The difference between the >three seems to, from a quick look, be their video encoding capabilities. >Is that correct? > Yes. it is correct. It seems like you have forgot a chip called CV1801B, which has 128MB RAM. But I see no board with this soc, so at now it is not necessary to care it.
> >>On Sun, Oct 01, 2023 at 06:34:21AM +0800, Inochi Amaoto wrote: >>> Hi, Jisheng >> >>>> Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. >> >>> >>> You add the clint dt-bindings of CV1800B clint, but I don't see the clint >>> node in this dt. The SBI needs this clint node to provide timer for linux. >>> AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader >>> may load the linux dt and pass it to the SBI. I think it is better to add >>> the clint node. >> >>> In addition, please separate the peripheral node to a different file, which >>> can be reused by both the CV1800 series and CV1810 series. >> >>How do these SoCs differ? > >AFAIK, the most peripheral of CV1800 and CV1810 are the same. there are >only a few difference between CV1800 and CV1810: >1. CV1810 have mmc interrupt, but CV1800 have none >2. CV1810 have more RAM and a more powerful TPU. >3. Some models of CV1810 support I2S. > >Also is some you have already mentioned, the video capabilities (including >encoding, output steam number, input steam number) are different. > >The only board with a CV1800 soc is Huashan Pi (CV1812H). > A mistake, I mean CV1810 soc, not the CV1800 one. >>Documentation seems rather lacking, but I was able to find something on >>github that suggests there is also a cv180zb. The difference between the >>three seems to, from a quick look, be their video encoding capabilities. >>Is that correct? >> > >Yes. it is correct. >It seems like you have forgot a chip called CV1801B, which has 128MB >RAM. But I see no board with this soc, so at now it is not necessary to >care it. > >
On Sat, Sep 30, 2023 at 08:39:36PM +0800, Jisheng Zhang wrote: > Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ > 1 file changed, 117 insertions(+) > create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > new file mode 100644 > index 000000000000..8829bebaa017 > --- /dev/null > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -0,0 +1,117 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "sophgo,cv1800b"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus: cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <25000000>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <512>; > + d-cache-size = <65536>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > + "zifencei", "zihpm"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + osc: oscillator { > + compatible = "fixed-clock"; > + clock-output-names = "osc_25m"; > + #clock-cells = <0>; > + }; Is this a stub that will later be replaced by a real clock controller node, or is this actually a fixed oscillator? If it is the former, could you add it to the commit message if there is a respin? Thanks, Conor.
On Sun, Oct 01, 2023 at 08:22:04PM +0800, Inochi Amaoto wrote: > > > >>On Sun, Oct 01, 2023 at 06:34:21AM +0800, Inochi Amaoto wrote: > >>> Hi, Jisheng > >> > >>>> Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > >> > >>> > >>> You add the clint dt-bindings of CV1800B clint, but I don't see the clint > >>> node in this dt. The SBI needs this clint node to provide timer for linux. > >>> AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader > >>> may load the linux dt and pass it to the SBI. I think it is better to add > >>> the clint node. > >> > >>> In addition, please separate the peripheral node to a different file, which > >>> can be reused by both the CV1800 series and CV1810 series. > >> > >>How do these SoCs differ? > > > >AFAIK, the most peripheral of CV1800 and CV1810 are the same. there are > >only a few difference between CV1800 and CV1810: > >1. CV1810 have mmc interrupt, but CV1800 have none > >2. CV1810 have more RAM and a more powerful TPU. > >3. Some models of CV1810 support I2S. > > > >Also is some you have already mentioned, the video capabilities (including > >encoding, output steam number, input steam number) are different. > > > >The only board with a CV1800 soc is Huashan Pi (CV1812H). > > > > A mistake, I mean CV1810 soc, not the CV1800 one. > > >>Documentation seems rather lacking, but I was able to find something on > >>github that suggests there is also a cv180zb. The difference between the > >>three seems to, from a quick look, be their video encoding capabilities. > >>Is that correct? > >> > > > >Yes. it is correct. > >It seems like you have forgot a chip called CV1801B, which has 128MB > >RAM. But I see no board with this soc, so at now it is not necessary to > >care it. FWIW, I do not mind if the properties are left inside a CV1800B specific file, and moved out at a later date if/when someone actually upstreams support for a board with that SoC.
On Sat, Sep 30, 2023 at 08:39:36PM +0800, Jisheng Zhang wrote: > + plic: interrupt-controller@70000000 { > + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; This fails dtbs_check, the compatible you added to the binding is cv1800-plic. > + reg = <0x70000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <101>; > + };
在 2023/9/30 20:39, Jisheng Zhang 写道: > Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ > 1 file changed, 117 insertions(+) > create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi Hi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by different people and even in sophgo, they are two independent projects(sg2042 is target for HPC and cv180x is target for embeded device). To facilitate future management and review, I recommend registering the maintainer information in two entries in MAINTAINERS. The example is as follows: ``` SOPHGO CV180X DEVICETREES M: Jisheng Zhang <jszhang@kernel.org> F: arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts F: arch/riscv/boot/dts/sophgo/cv1800b.dtsi SOPHGO SG2042 DEVICETREES M: Chao Wei <chao.wei@sophgo.com> M: Chen Wang <unicornxw@gmail.com> S: Maintained F: arch/riscv/boot/dts/sophgo/Makefile F: arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi F: arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts F: arch/riscv/boot/dts/sophgo/sg2042.dtsi F: Documentation/devicetree/bindings/riscv/sophgo.yaml ``` For Makefile and sophgo.yaml such common files, just keep in sg2042 entry should be fine. @Conor, what do you think? Thanks, Chen > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > new file mode 100644 > index 000000000000..8829bebaa017 > --- /dev/null > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -0,0 +1,117 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "sophgo,cv1800b"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus: cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <25000000>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <512>; > + d-cache-size = <65536>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > + "zifencei", "zihpm"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + osc: oscillator { > + compatible = "fixed-clock"; > + clock-output-names = "osc_25m"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <1>; > + #size-cells = <1>; > + dma-noncoherent; > + ranges; > + > + uart0: serial@04140000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x04140000 0x100>; > + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart1: serial@04150000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x04150000 0x100>; > + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart2: serial@04160000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x04160000 0x100>; > + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart3: serial@04170000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x04170000 0x100>; > + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart4: serial@041c0000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x041c0000 0x100>; > + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + plic: interrupt-controller@70000000 { > + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > + reg = <0x70000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <101>; > + }; > + }; > +};
On 04/10/2023 09:23, Chen Wang wrote: > > 在 2023/9/30 20:39, Jisheng Zhang 写道: >> Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. >> >> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> >> --- >> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ >> 1 file changed, 117 insertions(+) >> create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > Hi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by > different people and even in sophgo, they are two independent > projects(sg2042 is target for HPC and cv180x is target for embeded > device). To facilitate future management and review, I recommend > registering the maintainer information in two entries in MAINTAINERS. > The example is as follows: > > ``` > > SOPHGO CV180X DEVICETREES > M: Jisheng Zhang <jszhang@kernel.org> > F: arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts > F: arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > SOPHGO SG2042 DEVICETREES > M: Chao Wei <chao.wei@sophgo.com> > M: Chen Wang <unicornxw@gmail.com> > S: Maintained > F: arch/riscv/boot/dts/sophgo/Makefile > F: arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > F: arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts > F: arch/riscv/boot/dts/sophgo/sg2042.dtsi > F: Documentation/devicetree/bindings/riscv/sophgo.yaml > ``` > > For Makefile and sophgo.yaml such common files, just keep in sg2042 > entry should be fine. > > @Conor, what do you think? We do no have usually per-board maintainer entries (with few exceptions). I strongly prefer this one instead: https://lore.kernel.org/all/829b122da52482707b783dc3d93d3ff0179cb0ca.camel@perches.com/ Best regards, Krzysztof
On Wed, Oct 04, 2023 at 09:57:33AM +0200, Krzysztof Kozlowski wrote: > On 04/10/2023 09:23, Chen Wang wrote: > > > > 在 2023/9/30 20:39, Jisheng Zhang 写道: > >> Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > >> > >> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > >> --- > >> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ > >> 1 file changed, 117 insertions(+) > >> create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > > > Hi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by > > different people and even in sophgo, they are two independent > > projects(sg2042 is target for HPC and cv180x is target for embeded > > device). To facilitate future management and review, I recommend > > registering the maintainer information in two entries in MAINTAINERS. > > The example is as follows: > > > > ``` > > > > SOPHGO CV180X DEVICETREES > > M: Jisheng Zhang <jszhang@kernel.org> > > F: arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts > > F: arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > > > SOPHGO SG2042 DEVICETREES > > M: Chao Wei <chao.wei@sophgo.com> > > M: Chen Wang <unicornxw@gmail.com> > > S: Maintained > > F: arch/riscv/boot/dts/sophgo/Makefile > > F: arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > > F: arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts > > F: arch/riscv/boot/dts/sophgo/sg2042.dtsi > > F: Documentation/devicetree/bindings/riscv/sophgo.yaml > > ``` > > > > For Makefile and sophgo.yaml such common files, just keep in sg2042 > > entry should be fine. > > > > @Conor, what do you think? > > We do no have usually per-board maintainer entries (with few > exceptions). I strongly prefer this one instead: > > https://lore.kernel.org/all/829b122da52482707b783dc3d93d3ff0179cb0ca.camel@perches.com/ I don't like the suggestion here for a different reason! While I'm fine with having some per-board SoC maintainers, esp. since the cv1800 stuff is very different to the sg2042, I want to see someone step up to apply the patches for the whole arch/riscv/boot/dts/sophgo/ directory once more comfortable with the process, not reduce the entry to cover just the 64 core SoC. Thanks, Conor.
在 2023/10/4 17:13, Conor Dooley 写道: > On Wed, Oct 04, 2023 at 09:57:33AM +0200, Krzysztof Kozlowski wrote: >> On 04/10/2023 09:23, Chen Wang wrote: >>> 在 2023/9/30 20:39, Jisheng Zhang 写道: >>>> Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. >>>> >>>> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> >>>> --- >>>> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ >>>> 1 file changed, 117 insertions(+) >>>> create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>> Hi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by >>> different people and even in sophgo, they are two independent >>> projects(sg2042 is target for HPC and cv180x is target for embeded >>> device). To facilitate future management and review, I recommend >>> registering the maintainer information in two entries in MAINTAINERS. >>> The example is as follows: >>> >>> ``` >>> >>> SOPHGO CV180X DEVICETREES >>> M: Jisheng Zhang <jszhang@kernel.org> >>> F: arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts >>> F: arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>> >>> SOPHGO SG2042 DEVICETREES >>> M: Chao Wei <chao.wei@sophgo.com> >>> M: Chen Wang <unicornxw@gmail.com> >>> S: Maintained >>> F: arch/riscv/boot/dts/sophgo/Makefile >>> F: arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi >>> F: arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts >>> F: arch/riscv/boot/dts/sophgo/sg2042.dtsi >>> F: Documentation/devicetree/bindings/riscv/sophgo.yaml >>> ``` >>> >>> For Makefile and sophgo.yaml such common files, just keep in sg2042 >>> entry should be fine. >>> >>> @Conor, what do you think? >> We do no have usually per-board maintainer entries (with few >> exceptions). I strongly prefer this one instead: >> >> https://lore.kernel.org/all/829b122da52482707b783dc3d93d3ff0179cb0ca.camel@perches.com/ > I don't like the suggestion here for a different reason! While I'm fine > with having some per-board SoC maintainers, esp. since the cv1800 stuff > is very different to the sg2042, I want to see someone step up to apply > the patches for the whole arch/riscv/boot/dts/sophgo/ directory once more > comfortable with the process, not reduce the entry to cover just the 64 > core SoC. > > Thanks, > Conor. Thanks, Conor and Krzystof. Agree with you, it would be better to keep only one entry for arch/riscv/boot/dts/sophgo/ directory. I will discuss with other people working on sophgo and specify a unified maintenance task to maintain files under it.
On Mon, Oct 02, 2023 at 01:09:38PM +0100, Conor Dooley wrote: > On Sat, Sep 30, 2023 at 08:39:36PM +0800, Jisheng Zhang wrote: > > Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ > > 1 file changed, 117 insertions(+) > > create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > new file mode 100644 > > index 000000000000..8829bebaa017 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > @@ -0,0 +1,117 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + compatible = "sophgo,cv1800b"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus: cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + timebase-frequency = <25000000>; > > + > > + cpu0: cpu@0 { > > + compatible = "thead,c906", "riscv"; > > + device_type = "cpu"; > > + reg = <0>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <512>; > > + d-cache-size = <65536>; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <32768>; > > + mmu-type = "riscv,sv39"; > > + riscv,isa = "rv64imafdc"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > > + "zifencei", "zihpm"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + }; > > + > > + osc: oscillator { > > + compatible = "fixed-clock"; > > + clock-output-names = "osc_25m"; > > + #clock-cells = <0>; > > + }; > > Is this a stub that will later be replaced by a real clock controller > node, or is this actually a fixed oscillator? If it is the former, could Hi Conor, This is a real 25MHZ oscillator. Thanks
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file mode 100644 index 000000000000..8829bebaa017 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@04140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@04150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@04160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@04170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@041c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + }; +};
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi