| Message ID | 20231003042215.142678-3-shravan.chippa@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dma: sf-pdma: various sf-pdma updates for the mpfs platform | expand |
On Tue, Oct 03, 2023 at 09:52:13AM +0530, shravan chippa wrote: > From: Shravan Chippa <shravan.chippa@microchip.com> > > Add new compatible name microchip,mpfs-pdma to support > out of order dma transfers > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com> > --- > .../bindings/dma/sifive,fu540-c000-pdma.yaml | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > index a1af0b906365..974467c4bacb 100644 > --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > @@ -27,10 +27,14 @@ allOf: > > properties: > compatible: > - items: > - - enum: > - - sifive,fu540-c000-pdma > - - const: sifive,pdma0 > + oneOf: > + - items: > + - const: microchip,mpfs-pdma # Microchip out of order DMA transfer > + - const: sifive,fu540-c000-pdma # Sifive in-order DMA transfer This doesn't really make sense. microchip,mpfs-pdma is compatible with sifive,fu540-c000-pdma and sifive,fu540-c000-pdma is compatible with sifive,pdma0, but microchip,mpfs-pdma is not compatible with sifive,pdma0? (Or replace "compatible with" with "a superset of") Any fallback is only useful if an OS only understanding the fallback will work with the h/w. Does this h/w work without the driver changes? Rob
On Wed, Oct 04, 2023 at 08:30:21AM -0500, Rob Herring wrote: > On Tue, Oct 03, 2023 at 09:52:13AM +0530, shravan chippa wrote: > > From: Shravan Chippa <shravan.chippa@microchip.com> > > > > Add new compatible name microchip,mpfs-pdma to support > > out of order dma transfers > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com> > > --- > > .../bindings/dma/sifive,fu540-c000-pdma.yaml | 12 ++++++++---- > > 1 file changed, 8 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > index a1af0b906365..974467c4bacb 100644 > > --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > @@ -27,10 +27,14 @@ allOf: > > > > properties: > > compatible: > > - items: > > - - enum: > > - - sifive,fu540-c000-pdma > > - - const: sifive,pdma0 > > + oneOf: > > + - items: > > + - const: microchip,mpfs-pdma # Microchip out of order DMA transfer > > + - const: sifive,fu540-c000-pdma # Sifive in-order DMA transfer IIRC I asked for the comments here to be removed on the previous version, and my r-b was conditional on that. The device specific compatible has merit outside of the ordering, which may just be a software policy decision. > This doesn't really make sense. microchip,mpfs-pdma is compatible with > sifive,fu540-c000-pdma and sifive,fu540-c000-pdma is compatible with > sifive,pdma0, but microchip,mpfs-pdma is not compatible with > sifive,pdma0? (Or replace "compatible with" with "a superset of") TBH, I am not sure why it was done this way. Probably because the driver contains both sifive,pdma0 and sifive,fu540-c000-pdma. Doing compatible = "microchip,mpfs-pdma", "sifive,fu540-c000-pdma", "sifive,pdma0"; thing would be fine. > Any fallback is only useful if an OS only understanding the fallback > will work with the h/w. Does this h/w work without the driver changes? Yes. I've been hoping that someone from SiFive would come along, and in response to this patchset, tell us _why_ the driver does not make use of out-of-order transfers to begin with. Thanks, Conor.
Hi, > -----Original Message----- > From: Conor Dooley <conor@kernel.org> > Sent: Thursday, October 5, 2023 4:24 PM > To: Rob Herring <robh@kernel.org> > Cc: shravan Chippa - I35088 <Shravan.Chippa@microchip.com>; > green.wan@sifive.com; vkoul@kernel.org; krzysztof.kozlowski+dt@linaro.org; > palmer@dabbelt.com; paul.walmsley@sifive.com; conor+dt@kernel.org; > dmaengine@vger.kernel.org; devicetree@vger.kernel.org; linux- > riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Nagasuresh Relli - I67208 > <Nagasuresh.Relli@microchip.com>; Praveen Kumar - I30718 > <Praveen.Kumar@microchip.com>; Conor Dooley - M52691 > <Conor.Dooley@microchip.com> > Subject: Re: [PATCH v2 2/4] dt-bindings: dma: sf-pdma: add new compatible > name > > On Wed, Oct 04, 2023 at 08:30:21AM -0500, Rob Herring wrote: > > On Tue, Oct 03, 2023 at 09:52:13AM +0530, shravan chippa wrote: > > > From: Shravan Chippa <shravan.chippa@microchip.com> > > > > > > Add new compatible name microchip,mpfs-pdma to support out of order > > > dma transfers > > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com> > > > --- > > > .../bindings/dma/sifive,fu540-c000-pdma.yaml | 12 ++++++++---- > > > 1 file changed, 8 insertions(+), 4 deletions(-) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > > b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > > index a1af0b906365..974467c4bacb 100644 > > > --- > > > a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > > +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.y > > > +++ aml > > > @@ -27,10 +27,14 @@ allOf: > > > > > > properties: > > > compatible: > > > - items: > > > - - enum: > > > - - sifive,fu540-c000-pdma > > > - - const: sifive,pdma0 > > > + oneOf: > > > + - items: > > > + - const: microchip,mpfs-pdma # Microchip out of order DMA transfer > > > + - const: sifive,fu540-c000-pdma # Sifive in-order DMA > > > + transfer > > IIRC I asked for the comments here to be removed on the previous version, and > my r-b was conditional on that. > The device specific compatible has merit outside of the ordering, which may just > be a software policy decision. > > > This doesn't really make sense. microchip,mpfs-pdma is compatible with > > sifive,fu540-c000-pdma and sifive,fu540-c000-pdma is compatible with > > sifive,pdma0, but microchip,mpfs-pdma is not compatible with > > sifive,pdma0? (Or replace "compatible with" with "a superset of") > > TBH, I am not sure why it was done this way. Probably because the driver > contains both sifive,pdma0 and sifive,fu540-c000-pdma. Doing compatible = > "microchip,mpfs-pdma", "sifive,fu540-c000-pdma", "sifive,pdma0"; thing would > be fine. > > > Any fallback is only useful if an OS only understanding the fallback > > will work with the h/w. Does this h/w work without the driver changes? > > Yes. > I've been hoping that someone from SiFive would come along, and in response to > this patchset, tell us _why_ the driver does not make use of out-of-order transfers > to begin with. > I am also expecting a replay someone from SiFive The out-of-order should work with other RISC-V platforms also. I will try to send V3 with the below changes (just adding a new compatible name) **************************** --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -29,6 +29,7 @@ properties: compatible: items: - enum: + - microchip,mpfs-pdma - sifive,fu540-c000-pdma - const: sifive,pdma0 description: *************************** Device tree patch ***************************** --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -221,7 +221,7 @@ plic: interrupt-controller@c000000 { }; pdma: dma-controller@3000000 { - compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; + compatible = "microchip,mpfs-pdma", "sifive,fu540-c000-pdma", "sifive,pdma0"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; interrupts = <5 6>, <7 8>, <9 10>, <11 12>; *************************** Thanks, Shravan > Thanks, > Conor.
On Thu, Oct 12, 2023 at 09:22:17AM +0000, Shravan.Chippa@microchip.com wrote: > Hi, > > > -----Original Message----- > > From: Conor Dooley <conor@kernel.org> > > Sent: Thursday, October 5, 2023 4:24 PM > > To: Rob Herring <robh@kernel.org> > > Cc: shravan Chippa - I35088 <Shravan.Chippa@microchip.com>; > > green.wan@sifive.com; vkoul@kernel.org; krzysztof.kozlowski+dt@linaro.org; > > palmer@dabbelt.com; paul.walmsley@sifive.com; conor+dt@kernel.org; > > dmaengine@vger.kernel.org; devicetree@vger.kernel.org; linux- > > riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Nagasuresh Relli - I67208 > > <Nagasuresh.Relli@microchip.com>; Praveen Kumar - I30718 > > <Praveen.Kumar@microchip.com>; Conor Dooley - M52691 > > <Conor.Dooley@microchip.com> > > Subject: Re: [PATCH v2 2/4] dt-bindings: dma: sf-pdma: add new compatible > > name > > > > On Wed, Oct 04, 2023 at 08:30:21AM -0500, Rob Herring wrote: > > > On Tue, Oct 03, 2023 at 09:52:13AM +0530, shravan chippa wrote: > > > > From: Shravan Chippa <shravan.chippa@microchip.com> > > > > > > > > Add new compatible name microchip,mpfs-pdma to support out of order > > > > dma transfers > > > > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > > Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com> > > > > --- > > > > .../bindings/dma/sifive,fu540-c000-pdma.yaml | 12 ++++++++---- > > > > 1 file changed, 8 insertions(+), 4 deletions(-) > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > > > b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > > > index a1af0b906365..974467c4bacb 100644 > > > > --- > > > > a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > > > > +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.y > > > > +++ aml > > > > @@ -27,10 +27,14 @@ allOf: > > > > > > > > properties: > > > > compatible: > > > > - items: > > > > - - enum: > > > > - - sifive,fu540-c000-pdma > > > > - - const: sifive,pdma0 > > > > + oneOf: > > > > + - items: > > > > + - const: microchip,mpfs-pdma # Microchip out of order DMA transfer > > > > + - const: sifive,fu540-c000-pdma # Sifive in-order DMA > > > > + transfer > > > > IIRC I asked for the comments here to be removed on the previous version, and > > my r-b was conditional on that. > > The device specific compatible has merit outside of the ordering, which may just > > be a software policy decision. > > > > > This doesn't really make sense. microchip,mpfs-pdma is compatible with > > > sifive,fu540-c000-pdma and sifive,fu540-c000-pdma is compatible with > > > sifive,pdma0, but microchip,mpfs-pdma is not compatible with > > > sifive,pdma0? (Or replace "compatible with" with "a superset of") > > > > TBH, I am not sure why it was done this way. Probably because the driver > > contains both sifive,pdma0 and sifive,fu540-c000-pdma. Doing compatible = > > "microchip,mpfs-pdma", "sifive,fu540-c000-pdma", "sifive,pdma0"; thing would > > be fine. > > > > > Any fallback is only useful if an OS only understanding the fallback > > > will work with the h/w. Does this h/w work without the driver changes? > > > > Yes. > > I've been hoping that someone from SiFive would come along, and in response to > > this patchset, tell us _why_ the driver does not make use of out-of-order transfers > > to begin with. > > > > I am also expecting a replay someone from SiFive > The out-of-order should work with other RISC-V platforms also. > > I will try to send V3 with the below changes (just adding a new compatible name) > > **************************** > --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > @@ -29,6 +29,7 @@ properties: > compatible: > items: > - enum: > + - microchip,mpfs-pdma > - sifive,fu540-c000-pdma > - const: sifive,pdma0 > description: > *************************** > > Device tree patch > ***************************** > --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi > @@ -221,7 +221,7 @@ plic: interrupt-controller@c000000 { > }; > pdma: dma-controller@3000000 { > - compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; > + compatible = "microchip,mpfs-pdma", "sifive,fu540-c000-pdma", "sifive,pdma0"; This is gonna produce dtbs_check complaints. Your binding change only permits `compatible = "microchip,mpfs-pdma", "sifive,pdma0";` Cheers, Conor. > reg = <0x0 0x3000000 0x0 0x8000>; > interrupt-parent = <&plic>; > interrupts = <5 6>, <7 8>, <9 10>, <11 12>; > ***************************
Hi Conor, On 2023-10-05 5:54 AM, Conor Dooley wrote: > On Wed, Oct 04, 2023 at 08:30:21AM -0500, Rob Herring wrote: >> Any fallback is only useful if an OS only understanding the fallback >> will work with the h/w. Does this h/w work without the driver changes? > > Yes. > I've been hoping that someone from SiFive would come along, and in > response to this patchset, tell us _why_ the driver does not make use of > out-of-order transfers to begin with. I have raised this question internally. So far I have not seen anything to suggest we need strictly-ordered transfers either, but I still need to confirm this. Regards, Samuel
diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml index a1af0b906365..974467c4bacb 100644 --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -27,10 +27,14 @@ allOf: properties: compatible: - items: - - enum: - - sifive,fu540-c000-pdma - - const: sifive,pdma0 + oneOf: + - items: + - const: microchip,mpfs-pdma # Microchip out of order DMA transfer + - const: sifive,fu540-c000-pdma # Sifive in-order DMA transfer + - items: + - enum: + - sifive,fu540-c000-pdma + - const: sifive,pdma0 description: Should be "sifive,<chip>-pdma" and "sifive,pdma<version>". Supported compatible strings are -