Show patches with: Submitter = Samuel Holland       |    State = Action Required       |    Archived = No       |   29 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[4/4] cache: sifive_ccache: Add EDAC and PMU as auxiliary devices cache: sifive_ccache: Auxiliary device support - - - --1 2024-04-10 Samuel Holland conchuod New
[3/4] cache: sifive_ccache: Export base address for child drivers cache: sifive_ccache: Auxiliary device support - - - --1 2024-04-10 Samuel Holland conchuod New
[2/4] cache: sifive_ccache: Use of_iomap() helper cache: sifive_ccache: Auxiliary device support - - - --1 2024-04-10 Samuel Holland conchuod New
[1/4] cache: sifive_ccache: Silence unused variable warning cache: sifive_ccache: Auxiliary device support - - - --1 2024-04-10 Samuel Holland conchuod New
[v2,7/7] riscv: Remove extra variable in patch_text_nosync() riscv: Various text patching improvements - 1 - --1 2024-03-27 Samuel Holland New
[v2,6/7] riscv: Use offset_in_page() in text patching functions riscv: Various text patching improvements - 1 - --1 2024-03-27 Samuel Holland New
[v2,5/7] riscv: Pass patch_text() the length in bytes riscv: Various text patching improvements - 1 - --1 2024-03-27 Samuel Holland New
[v2,4/7] riscv: Simplify text patching loops riscv: Various text patching improvements - 1 - --1 2024-03-27 Samuel Holland New
[v2,3/7] riscv: kprobes: Use patch_text_nosync() for insn slots riscv: Various text patching improvements - 1 - --1 2024-03-27 Samuel Holland New
[v2,2/7] riscv: jump_label: Simplify assembly syntax riscv: Various text patching improvements - 1 - --1 2024-03-27 Samuel Holland New
[v2,1/7] riscv: jump_label: Batch icache maintenance riscv: Various text patching improvements - 1 - --1 2024-03-27 Samuel Holland New
[v2,2/2] riscv: Define TASK_SIZE_MAX for __access_ok() riscv: access_ok() optimization - 2 - 13-- 2024-03-27 Samuel Holland New
[v2,1/2] riscv: Remove PGDIR_SIZE_L3 and TASK_SIZE_MIN riscv: access_ok() optimization 1 1 - 13-- 2024-03-27 Samuel Holland New
[v6,13/13] riscv: mm: Always use an ASID to flush mm contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,12/13] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,11/13] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,10/13] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2024-03-27 Samuel Holland New
[v6,06/13] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - 2 - 13-- 2024-03-27 Samuel Holland New
[v6,05/13] riscv: Only send remote fences when some other CPU is online riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,04/13] riscv: mm: Broadcast kernel TLB flushes only when needed riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,03/13] riscv: Use IPIs for remote cache/TLB flushes by default riscv: ASID-related and UP-related TLB flush enhancements - 2 - 13-- 2024-03-27 Samuel Holland New
[v6,02/13] riscv: Factor out page table TLB synchronization riscv: ASID-related and UP-related TLB flush enhancements - 1 - 13-- 2024-03-27 Samuel Holland New
[v6,01/13] riscv: Flush the instruction cache during SMP bringup riscv: ASID-related and UP-related TLB flush enhancements - 1 - 121- 2024-03-27 Samuel Holland New
[v2] riscv: Add tracepoints for SBI calls and returns [v2] riscv: Add tracepoints for SBI calls and returns - 1 - 121- 2024-03-21 Samuel Holland New
riscv: Define TASK_SIZE_MAX for __access_ok() riscv: Define TASK_SIZE_MAX for __access_ok() - 1 - 13-- 2024-03-13 Samuel Holland New
clocksource/drivers/timer-riscv: Drop extra CSR write clocksource/drivers/timer-riscv: Drop extra CSR write - - - 13-- 2024-03-12 Samuel Holland New