diff mbox series

[v2,15/45] target/hppa: Use umax in do_ibranch_priv

Message ID 20240513074717.130949-16-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show
Series target/hppa: Misc improvements | expand

Commit Message

Richard Henderson May 13, 2024, 7:46 a.m. UTC
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Philippe Mathieu-Daudé May 13, 2024, 11:18 a.m. UTC | #1
Hi Richard,

On 13/5/24 09:46, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/hppa/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index ae66068123..22935f4645 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -1981,7 +1981,7 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset)
>           dest = tcg_temp_new_i64();
>           tcg_gen_andi_i64(dest, offset, -4);
>           tcg_gen_ori_i64(dest, dest, ctx->privilege);
> -        tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset);
> +        tcg_gen_umax_i64(dest, dest, offset);

Isn't tcg_gen_umax_i64(dest, dest, offset) equal to:

     tcg_gen_movcond_i64(TCG_COND_GEU, dest, dest, offset, dest, offset);

?

>           break;
>       }
>       return dest;
Richard Henderson May 13, 2024, 1:23 p.m. UTC | #2
On 5/13/24 13:18, Philippe Mathieu-Daudé wrote:
> Hi Richard,
> 
> On 13/5/24 09:46, Richard Henderson wrote:
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/hppa/translate.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
>> index ae66068123..22935f4645 100644
>> --- a/target/hppa/translate.c
>> +++ b/target/hppa/translate.c
>> @@ -1981,7 +1981,7 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset)
>>           dest = tcg_temp_new_i64();
>>           tcg_gen_andi_i64(dest, offset, -4);
>>           tcg_gen_ori_i64(dest, dest, ctx->privilege);
>> -        tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset);
>> +        tcg_gen_umax_i64(dest, dest, offset);
> 
> Isn't tcg_gen_umax_i64(dest, dest, offset) equal to:
> 
>      tcg_gen_movcond_i64(TCG_COND_GEU, dest, dest, offset, dest, offset);
> 
> ?

Yes, but I think it is clearer to use max.
At some point we might add min/max opcodes to tcg too.


r~
Philippe Mathieu-Daudé May 13, 2024, 2:15 p.m. UTC | #3
On 13/5/24 15:23, Richard Henderson wrote:
> On 5/13/24 13:18, Philippe Mathieu-Daudé wrote:
>> Hi Richard,
>>
>> On 13/5/24 09:46, Richard Henderson wrote:
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>>   target/hppa/translate.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
>>> index ae66068123..22935f4645 100644
>>> --- a/target/hppa/translate.c
>>> +++ b/target/hppa/translate.c
>>> @@ -1981,7 +1981,7 @@ static TCGv_i64 do_ibranch_priv(DisasContext 
>>> *ctx, TCGv_i64 offset)
>>>           dest = tcg_temp_new_i64();
>>>           tcg_gen_andi_i64(dest, offset, -4);
>>>           tcg_gen_ori_i64(dest, dest, ctx->privilege);
>>> -        tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, 
>>> offset);
>>> +        tcg_gen_umax_i64(dest, dest, offset);
>>
>> Isn't tcg_gen_umax_i64(dest, dest, offset) equal to:
>>
>>      tcg_gen_movcond_i64(TCG_COND_GEU, dest, dest, offset, dest, offset);
>>
>> ?
> 
> Yes, but I think it is clearer to use max.

OK, maybe mention it in commit description to clear doubts?

> At some point we might add min/max opcodes to tcg too.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ae66068123..22935f4645 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1981,7 +1981,7 @@  static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset)
         dest = tcg_temp_new_i64();
         tcg_gen_andi_i64(dest, offset, -4);
         tcg_gen_ori_i64(dest, dest, ctx->privilege);
-        tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset);
+        tcg_gen_umax_i64(dest, dest, offset);
         break;
     }
     return dest;