diff mbox series

[2/4] riscv: entry: Balance vector context nesting

Message ID 20240530001733.1407654-3-samuel.holland@sifive.com (mailing list archive)
State Changes Requested
Headers show
Series riscv: Frame pointer fixes and enhancements | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-2-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh
conchuod/patch-2-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh
conchuod/patch-2-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh
conchuod/patch-2-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-2-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-2-test-6 success .github/scripts/patches/tests/checkpatch.sh
conchuod/patch-2-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh
conchuod/patch-2-test-8 success .github/scripts/patches/tests/header_inline.sh
conchuod/patch-2-test-9 success .github/scripts/patches/tests/kdoc.sh
conchuod/patch-2-test-10 success .github/scripts/patches/tests/module_param.sh
conchuod/patch-2-test-11 success .github/scripts/patches/tests/verify_fixes.sh
conchuod/patch-2-test-12 success .github/scripts/patches/tests/verify_signedoff.sh

Commit Message

Samuel Holland May 30, 2024, 12:15 a.m. UTC
Vector context management is the last thing done before jumping to C
code, so it should be the first thing done after returning from C code.
This also improves efficiency: riscv_v_context_nesting_end() clobbers
the saved value of the status CSR, so currently ret_from_exception()
must reload it. This is not necessary if riscv_v_context_nesting_end()
is called first.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/kernel/entry.S | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

Comments

Matthew Bystrin June 6, 2024, 9:36 p.m. UTC | #1
Hi! Thanks for the patch!

On Thu May 30, 2024 at 3:15 AM MSK, Samuel Holland wrote:
> Vector context management is the last thing done before jumping to C
> code, so it should be the first thing done after returning from C code.
> This also improves efficiency: riscv_v_context_nesting_end() clobbers
> the saved value of the status CSR, so currently ret_from_exception()
> must reload it. This is not necessary if riscv_v_context_nesting_end()
> is called first.

IIUC this patch do not improves efficiency by itself, because reload of CSR
stays in place.  What do think about applying here s1 register related changes
from the next patch?  Is it reasonable?  Or you can describe this patch in a
different way, like it makes preparations for efficiency improvements.
diff mbox series

Patch

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 4c5b22cb7381..d13d1aad7649 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -120,6 +120,11 @@  ASM_NOKPROBE(handle_exception)
  *  - ret_from_fork
  */
 SYM_CODE_START_NOALIGN(ret_from_exception)
+#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
+	move a0, sp
+	call riscv_v_context_nesting_end
+#endif
+
 	REG_L s0, PT_STATUS(sp)
 #ifdef CONFIG_RISCV_M_MODE
 	/* the MPP value is too large to be used as an immediate arg for addi */
@@ -143,10 +148,6 @@  SYM_CODE_START_NOALIGN(ret_from_exception)
 	 */
 	csrw CSR_SCRATCH, tp
 1:
-#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
-	move a0, sp
-	call riscv_v_context_nesting_end
-#endif
 	REG_L a0, PT_STATUS(sp)
 	/*
 	 * The current load reservation is effectively part of the processor's