| Message ID | 20241206055829.1059293-2-inochiama@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: Add bfloat16 instruction support | expand |
On 2024-12-05 11:58 PM, Inochi Amaoto wrote: > Add description for the BFloat16 precision Floating-Point ISA extension, > (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 > ("Added Chapter title to BF16") of the riscv-isa-manual. > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 9c7dd7e75e0c..0a1f1a76d129 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -329,6 +329,12 @@ properties: > instructions, as ratified in commit 056b6ff ("Zfa is ratified") of > riscv-isa-manual. > > + - const: zfbfmin > + description: > + The standard Zfbfmin extension which provides minimal support for > + 16-bit half-precision brain floating-point instructions, as ratified I think you mean "binary" here and in the entries below, not "brain". > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > - const: zfh > description: > The standard Zfh extension for 16-bit half-precision binary > @@ -525,6 +531,18 @@ properties: > in commit 6f702a2 ("Vector extensions are now ratified") of > riscv-v-spec. > > + - const: zvfbfmin > + description: > + The standard Zvfbfmin extension for minimal support for vectored > + 16-bit half-precision brain floating-point instructions, as ratified > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > + - const: zvfbfwma > + description: > + The standard Zvfbfwma extension for vectored half-precision brain > + floating-point widening multiply-accumulate instructions, as ratified > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > - const: zvfh > description: > The standard Zvfh extension for vectored half-precision > @@ -663,6 +681,33 @@ properties: > then: > contains: > const: zca > + # Zfbfmin depends on F > + - if: > + contains: > + const: zfbfmin > + then: > + contains: > + const: f > + # Zvfbfmin depends on V or Zve32f > + - if: > + contains: > + const: zvfbfmin > + then: > + oneOf: > + - contains: > + const: v > + - contains: > + const: zve32f > + # Zvfbfwma depends on Zfbfmin and Zvfbfmin > + - if: > + contains: > + const: zvfbfwma > + then: > + allOf: > + - contains: > + const: zfbfmin > + - contains: > + const: zvfbfmin > > allOf: > # Zcf extension does not exist on rv64
On 16 Dec 2024, at 22:00, Samuel Holland <samuel.holland@sifive.com> wrote: > > On 2024-12-05 11:58 PM, Inochi Amaoto wrote: >> Add description for the BFloat16 precision Floating-Point ISA extension, >> (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 >> ("Added Chapter title to BF16") of the riscv-isa-manual. >> >> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> >> Acked-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ >> 1 file changed, 45 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml >> index 9c7dd7e75e0c..0a1f1a76d129 100644 >> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml >> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml >> @@ -329,6 +329,12 @@ properties: >> instructions, as ratified in commit 056b6ff ("Zfa is ratified") of >> riscv-isa-manual. >> >> + - const: zfbfmin >> + description: >> + The standard Zfbfmin extension which provides minimal support for >> + 16-bit half-precision brain floating-point instructions, as ratified > > I think you mean "binary" here and in the entries below, not "brain”. No, that’s Zfhmin / FP16 / binary16, not Zfbfmin / BF16 / BFloat16? The B is for Brain as it came out of Google Brain. https://en.wikipedia.org/wiki/Bfloat16_floating-point_format Jess
On 2024-12-16 4:51 PM, Jessica Clarke wrote: > On 16 Dec 2024, at 22:00, Samuel Holland <samuel.holland@sifive.com> wrote: >> >> On 2024-12-05 11:58 PM, Inochi Amaoto wrote: >>> Add description for the BFloat16 precision Floating-Point ISA extension, >>> (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 >>> ("Added Chapter title to BF16") of the riscv-isa-manual. >>> >>> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> >>> Acked-by: Conor Dooley <conor.dooley@microchip.com> >>> --- >>> .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ >>> 1 file changed, 45 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml >>> index 9c7dd7e75e0c..0a1f1a76d129 100644 >>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml >>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml >>> @@ -329,6 +329,12 @@ properties: >>> instructions, as ratified in commit 056b6ff ("Zfa is ratified") of >>> riscv-isa-manual. >>> >>> + - const: zfbfmin >>> + description: >>> + The standard Zfbfmin extension which provides minimal support for >>> + 16-bit half-precision brain floating-point instructions, as ratified >> >> I think you mean "binary" here and in the entries below, not "brain”. > > No, that’s Zfhmin / FP16 / binary16, not Zfbfmin / BF16 / BFloat16? The > B is for Brain as it came out of Google Brain. > > https://en.wikipedia.org/wiki/Bfloat16_floating-point_format Ah, yes, I was the confused one here. Sorry for the noise.
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 9c7dd7e75e0c..0a1f1a76d129 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -329,6 +329,12 @@ properties: instructions, as ratified in commit 056b6ff ("Zfa is ratified") of riscv-isa-manual. + - const: zfbfmin + description: + The standard Zfbfmin extension which provides minimal support for + 16-bit half-precision brain floating-point instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary @@ -525,6 +531,18 @@ properties: in commit 6f702a2 ("Vector extensions are now ratified") of riscv-v-spec. + - const: zvfbfmin + description: + The standard Zvfbfmin extension for minimal support for vectored + 16-bit half-precision brain floating-point instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + + - const: zvfbfwma + description: + The standard Zvfbfwma extension for vectored half-precision brain + floating-point widening multiply-accumulate instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + - const: zvfh description: The standard Zvfh extension for vectored half-precision @@ -663,6 +681,33 @@ properties: then: contains: const: zca + # Zfbfmin depends on F + - if: + contains: + const: zfbfmin + then: + contains: + const: f + # Zvfbfmin depends on V or Zve32f + - if: + contains: + const: zvfbfmin + then: + oneOf: + - contains: + const: v + - contains: + const: zve32f + # Zvfbfwma depends on Zfbfmin and Zvfbfmin + - if: + contains: + const: zvfbfwma + then: + allOf: + - contains: + const: zfbfmin + - contains: + const: zvfbfmin allOf: # Zcf extension does not exist on rv64
Add description for the BFloat16 precision Floating-Point ISA extension, (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 ("Added Chapter title to BF16") of the riscv-isa-manual. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+)