| Message ID | 20250325141311.758787-4-emil.renner.berthing@canonical.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | ESWIN EIC7700 pinctrl driver | expand |
| Context | Check | Description |
|---|---|---|
| bjorn/pre-ci_am | fail | Failed to apply series |
On 2025-03-25 9:13 AM, Emil Renner Berthing wrote: > Add node for the pin controller on the ESWIN EIC7700 SoC and gpio-ranges > properties mapping GPIOs to pins. > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > --- > arch/riscv/boot/dts/eswin/eic7700.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi > index 9cef940f07e4..7226647919b7 100644 > --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi > +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi > @@ -312,6 +312,13 @@ porta: gpio-port@0 { > <324>, <325>, <326>, <327>, <328>, <329>, <330>, > <331>, <332>, <333>, <334>; > gpio-controller; > + gpio-ranges = <&pinctrl 0 12 1>, > + <&pinctrl 1 14 12>, > + <&pinctrl 13 1 4>, > + <&pinctrl 17 32 1>, > + <&pinctrl 18 40 5>, > + <&pinctrl 23 51 7>, > + <&pinctrl 30 68 2>; > ngpios = <32>; > #gpio-cells = <2>; > }; > @@ -320,6 +327,9 @@ portb: gpio-port@1 { > compatible = "snps,dw-apb-gpio-port"; > reg = <1>; > gpio-controller; > + gpio-ranges = <&pinctrl 0 70 3>, > + <&pinctrl 3 79 7>, > + <&pinctrl 10 89 22>; > ngpios = <32>; > #gpio-cells = <2>; > }; > @@ -328,6 +338,7 @@ portc: gpio-port@2 { > compatible = "snps,dw-apb-gpio-port"; > reg = <2>; > gpio-controller; > + gpio-ranges = <&pinctrl 0 111 32>; > ngpios = <32>; > #gpio-cells = <2>; > }; > @@ -336,9 +347,15 @@ portd: gpio-port@3 { > compatible = "snps,dw-apb-gpio-port"; > reg = <3>; > gpio-controller; > + gpio-ranges = <&pinctrl 0 143 16>; > ngpios = <16>; > #gpio-cells = <2>; > }; > }; > + > + pinctrl: pinctrl@51600080 { > + compatible = "eswin,eic7700-pinctrl"; > + reg = <0x0 0x51600080 0x0 0xff80>; Per the TRM, the MMIO range is 2M-128B large, so the size should be 0x1fff80. Other than that, the rest looks good (especially, the GPIO ranges match what I have), so: Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > + }; > }; > };
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index 9cef940f07e4..7226647919b7 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -312,6 +312,13 @@ porta: gpio-port@0 { <324>, <325>, <326>, <327>, <328>, <329>, <330>, <331>, <332>, <333>, <334>; gpio-controller; + gpio-ranges = <&pinctrl 0 12 1>, + <&pinctrl 1 14 12>, + <&pinctrl 13 1 4>, + <&pinctrl 17 32 1>, + <&pinctrl 18 40 5>, + <&pinctrl 23 51 7>, + <&pinctrl 30 68 2>; ngpios = <32>; #gpio-cells = <2>; }; @@ -320,6 +327,9 @@ portb: gpio-port@1 { compatible = "snps,dw-apb-gpio-port"; reg = <1>; gpio-controller; + gpio-ranges = <&pinctrl 0 70 3>, + <&pinctrl 3 79 7>, + <&pinctrl 10 89 22>; ngpios = <32>; #gpio-cells = <2>; }; @@ -328,6 +338,7 @@ portc: gpio-port@2 { compatible = "snps,dw-apb-gpio-port"; reg = <2>; gpio-controller; + gpio-ranges = <&pinctrl 0 111 32>; ngpios = <32>; #gpio-cells = <2>; }; @@ -336,9 +347,15 @@ portd: gpio-port@3 { compatible = "snps,dw-apb-gpio-port"; reg = <3>; gpio-controller; + gpio-ranges = <&pinctrl 0 143 16>; ngpios = <16>; #gpio-cells = <2>; }; }; + + pinctrl: pinctrl@51600080 { + compatible = "eswin,eic7700-pinctrl"; + reg = <0x0 0x51600080 0x0 0xff80>; + }; }; };
Add node for the pin controller on the ESWIN EIC7700 SoC and gpio-ranges properties mapping GPIOs to pins. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- arch/riscv/boot/dts/eswin/eic7700.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)