| Message ID | 1351241899-7870-5-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi 2012/10/26 Daniel Vetter <daniel.vetter@ffwll.ch>: > Atm we have a few funny issues where we enable/disable shared > pll clocks. To make it clear that we are not required to enable/ > disable the pch plls together with the other pch resources (and > so should keep it running when it's used by another pipe in > a shared pll configuration) add a comment. > > This note is lifted from "Graphics BSpec: vol4g North Display Engine > Registers [IVB], Display Mode Set Sequence", step 9.d. of the enable > sequence: > > "Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be > done anytime before enabling PCH transcoder)." > > Since fixing the pll sharing code to no longer disable shared plls > if they're still in use is more involved, let's just stick with the > comment for now. I'm not sure what's the problem with the current code. Could you please explain a little bit more? After a brief look at intel_enable_pch_pll and intel_disable_pch_pll it seems our code does try to check the pll refcount and behave correctly. I'm not an expert of the ILK PCH pll sharing code, so I may be missing something. > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/gpu/drm/i915/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index b19e3bb..aa80ecb 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3007,6 +3007,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) > /* For PCH output, training FDI link */ > dev_priv->display.fdi_link_train(crtc); > > + /* XXX: pch pll's can be enabled any time before we enable the PCH > + * transcoder, and we actually should do this to not upset any PCH > + * transcoder that already use the clock when we share it. */ > intel_enable_pch_pll(intel_crtc); > > if (HAS_PCH_LPT(dev)) { > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Sat, Oct 27, 2012 at 2:15 PM, Paulo Zanoni <przanoni@gmail.com> wrote: > I'm not sure what's the problem with the current code. Could you > please explain a little bit more? After a brief look at > intel_enable_pch_pll and intel_disable_pch_pll it seems our code does > try to check the pll refcount and behave correctly. I'm not an expert > of the ILK PCH pll sharing code, so I may be missing something. Indeed, the comment is at the wrong place, but I _did_ remember the code correctly: In get_pch_pll we unconditionally rewrite (and in doing so, disable) the pch_pll and reset pll->on, even when the pll is currently on and used already. We can't just fix this, since the lvds enable code _requires_ that the pll is off (otherwise the ldvs pin pair enabling will fail). So it's not that easy to fix. I'll update the comment. Thanks, Daniel
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b19e3bb..aa80ecb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3007,6 +3007,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) /* For PCH output, training FDI link */ dev_priv->display.fdi_link_train(crtc); + /* XXX: pch pll's can be enabled any time before we enable the PCH + * transcoder, and we actually should do this to not upset any PCH + * transcoder that already use the clock when we share it. */ intel_enable_pch_pll(intel_crtc); if (HAS_PCH_LPT(dev)) {
Atm we have a few funny issues where we enable/disable shared pll clocks. To make it clear that we are not required to enable/ disable the pch plls together with the other pch resources (and so should keep it running when it's used by another pipe in a shared pll configuration) add a comment. This note is lifted from "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 9.d. of the enable sequence: "Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling PCH transcoder)." Since fixing the pll sharing code to no longer disable shared plls if they're still in use is more involved, let's just stick with the comment for now. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+)