Message ID | 1353425264-3728-3-git-send-email-przanoni@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
> - * Account for spread spectrum to avoid > - * oversubscribing the link. Max center spread > - * is 2.5%; use 5% for safety's sake. > + * The spec says: > + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) Right, so the real question is: "Is that ok to not get the spread rate (maximum of how much we derive from the requested frequency) into account?" I believe it is, on average the frequency is what we set-up. Maybe Adam can shed more light on why he thought it was necessary? As a side note, the spec does not mention that at all.
Hi 2012/11/20 Damien Lespiau <damien.lespiau@intel.com>: >> - * Account for spread spectrum to avoid >> - * oversubscribing the link. Max center spread >> - * is 2.5%; use 5% for safety's sake. >> + * The spec says: >> + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) > > Right, so the real question is: "Is that ok to not get the spread rate > (maximum of how much we derive from the requested frequency) into > account?" Well, the spec does not say we need to do this. Also, I tested this patch on SNB and some modes that were moved from 3 to 2 lanes still work. > > I believe it is, on average the frequency is what we set-up. Maybe > Adam can shed more light on why he thought it was necessary? > > As a side note, the spec does not mention that at all. > > -- > Damien
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0102931..9940765 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5272,14 +5272,15 @@ static void ironlake_set_m_n(struct drm_crtc *crtc, if (!lane) { /* - * Account for spread spectrum to avoid - * oversubscribing the link. Max center spread - * is 2.5%; use 5% for safety's sake. + * The spec says: + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) */ - u32 bps = target_clock * intel_crtc->bpp * 21 / 20; - lane = bps / (link_bw * 8) + 1; + u32 bps = target_clock * intel_crtc->bpp; + lane = DIV_ROUND_UP(bps, (link_bw * 8)); } + DRM_DEBUG_KMS("Using %d FDI lanes on pipe %c\n", lane, + pipe_name(intel_crtc->pipe)); intel_crtc->fdi_lanes = lane; if (pixel_multiplier > 1)