| Message ID | 20190716115745.12585-24-jagan@amarulasolutions.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ram: rk3399: Add LPDDR4 support | expand |
On 2019/7/16 下午7:57, Jagan Teki wrote: > mode_sel assignment is based on dram type. > > In phy_io_config, already have vref setting based > on the dram type, so move this mode_sel assignment > on vref setting area. > > No functionality change. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/ram/rockchip/sdram_rk3399.c | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 711477188e..88fbfa440d 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -205,6 +205,7 @@ static int phy_io_config(const struct chan_info *chan, > vref_value_dq = 0x1f; > vref_mode_ac = 0x6; > vref_value_ac = 0x1f; > + mode_sel = 0x6; > } else if (params->base.dramtype == LPDDR3) { > if (params->base.odt == 1) { > vref_mode_dq = 0x5; /* LPDDR3 ODT */ > @@ -265,12 +266,14 @@ static int phy_io_config(const struct chan_info *chan, > } > vref_mode_ac = 0x2; > vref_value_ac = 0x1f; > + mode_sel = 0x0; > } else if (params->base.dramtype == DDR3) { > /* DDR3L */ > vref_mode_dq = 0x1; > vref_value_dq = 0x1f; > vref_mode_ac = 0x1; > vref_value_ac = 0x1f; > + mode_sel = 0x1; > } else { > debug("Unknown DRAM type.\n"); > return -EINVAL; > @@ -292,15 +295,6 @@ static int phy_io_config(const struct chan_info *chan, > /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ > clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); > > - if (params->base.dramtype == LPDDR4) > - mode_sel = 0x6; > - else if (params->base.dramtype == LPDDR3) > - mode_sel = 0x0; > - else if (params->base.dramtype == DDR3) > - mode_sel = 0x1; > - else > - return -EINVAL; > - > /* PHY_924 PHY_PAD_FDBK_DRIVE */ > clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); > /* PHY_926 PHY_PAD_DATA_DRIVE */
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 711477188e..88fbfa440d 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -205,6 +205,7 @@ static int phy_io_config(const struct chan_info *chan, vref_value_dq = 0x1f; vref_mode_ac = 0x6; vref_value_ac = 0x1f; + mode_sel = 0x6; } else if (params->base.dramtype == LPDDR3) { if (params->base.odt == 1) { vref_mode_dq = 0x5; /* LPDDR3 ODT */ @@ -265,12 +266,14 @@ static int phy_io_config(const struct chan_info *chan, } vref_mode_ac = 0x2; vref_value_ac = 0x1f; + mode_sel = 0x0; } else if (params->base.dramtype == DDR3) { /* DDR3L */ vref_mode_dq = 0x1; vref_value_dq = 0x1f; vref_mode_ac = 0x1; vref_value_ac = 0x1f; + mode_sel = 0x1; } else { debug("Unknown DRAM type.\n"); return -EINVAL; @@ -292,15 +295,6 @@ static int phy_io_config(const struct chan_info *chan, /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); - if (params->base.dramtype == LPDDR4) - mode_sel = 0x6; - else if (params->base.dramtype == LPDDR3) - mode_sel = 0x0; - else if (params->base.dramtype == DDR3) - mode_sel = 0x1; - else - return -EINVAL; - /* PHY_924 PHY_PAD_FDBK_DRIVE */ clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); /* PHY_926 PHY_PAD_DATA_DRIVE */
mode_sel assignment is based on dram type. In phy_io_config, already have vref setting based on the dram type, so move this mode_sel assignment on vref setting area. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/ram/rockchip/sdram_rk3399.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-)