[v3,24/57] ram: rk3399: Don't wait for PLL lock in lpddr4
diff mbox series

Message ID 20190716115745.12585-25-jagan@amarulasolutions.com
State New
Headers show
Series
  • ram: rk3399: Add LPDDR4 support
Related show

Commit Message

Jagan Teki July 16, 2019, 11:57 a.m. UTC
lpddr4 has PLL bypass mode during phy initialization phase,
which does all pll configurations.

So no need to wait explicitly during pctl config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

Comments

Kever Yang July 16, 2019, 1:12 p.m. UTC | #1
On 2019/7/16 下午7:57, Jagan Teki wrote:
> lpddr4 has PLL bypass mode during phy initialization phase,
> which does all pll configurations.
>
> So no need to wait explicitly during pctl config.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++----------
>   1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 88fbfa440d..023838a301 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -570,16 +570,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
>   	setbits_le32(&denali_pi[0], START);
>   	setbits_le32(&denali_ctl[0], START);
>   
> -	/* Waiting for phy DLL lock */
> -	while (1) {
> -		tmp = readl(&denali_phy[920]);
> -		tmp1 = readl(&denali_phy[921]);
> -		tmp2 = readl(&denali_phy[922]);
> -		if ((((tmp >> 16) & 0x1) == 0x1) &&
> -		    (((tmp1 >> 16) & 0x1) == 0x1) &&
> -		    (((tmp1 >> 0) & 0x1) == 0x1) &&
> -		    (((tmp2 >> 0) & 0x1) == 0x1))
> -			break;
> +	/**
> +	 * LPDDR4 use PLL bypass mode for init
> +	 * not need to wait for the PLL to lock
> +	 */
> +	if (params->base.dramtype != LPDDR4) {
> +		/* Waiting for phy DLL lock */
> +		while (1) {
> +			tmp = readl(&denali_phy[920]);
> +			tmp1 = readl(&denali_phy[921]);
> +			tmp2 = readl(&denali_phy[922]);
> +			if ((((tmp >> 16) & 0x1) == 0x1) &&
> +			    (((tmp1 >> 16) & 0x1) == 0x1) &&
> +			    (((tmp1 >> 0) & 0x1) == 0x1) &&
> +			    (((tmp2 >> 0) & 0x1) == 0x1))
> +				break;
> +		}
>   	}
>   
>   	copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);

Patch
diff mbox series

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 88fbfa440d..023838a301 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -570,16 +570,22 @@  static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	setbits_le32(&denali_pi[0], START);
 	setbits_le32(&denali_ctl[0], START);
 
-	/* Waiting for phy DLL lock */
-	while (1) {
-		tmp = readl(&denali_phy[920]);
-		tmp1 = readl(&denali_phy[921]);
-		tmp2 = readl(&denali_phy[922]);
-		if ((((tmp >> 16) & 0x1) == 0x1) &&
-		    (((tmp1 >> 16) & 0x1) == 0x1) &&
-		    (((tmp1 >> 0) & 0x1) == 0x1) &&
-		    (((tmp2 >> 0) & 0x1) == 0x1))
-			break;
+	/**
+	 * LPDDR4 use PLL bypass mode for init
+	 * not need to wait for the PLL to lock
+	 */
+	if (params->base.dramtype != LPDDR4) {
+		/* Waiting for phy DLL lock */
+		while (1) {
+			tmp = readl(&denali_phy[920]);
+			tmp1 = readl(&denali_phy[921]);
+			tmp2 = readl(&denali_phy[922]);
+			if ((((tmp >> 16) & 0x1) == 0x1) &&
+			    (((tmp1 >> 16) & 0x1) == 0x1) &&
+			    (((tmp1 >> 0) & 0x1) == 0x1) &&
+			    (((tmp2 >> 0) & 0x1) == 0x1))
+				break;
+		}
 	}
 
 	copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);