| Message ID | 20191223173244.30742-4-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Prefer acronym for prefixes | expand |
On Mon, Dec 23, 2019 at 09:32:37AM -0800, Lucas De Marchi wrote: > We are currently using a mix of platform name and acronym to name the > functions. Let's prefer the acronym as it should be clear what platform > it's about and it's shorter, so it doesn't go over 80 columns in a few > cases. This converts haswell to hsw where appropriate. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Acked-by: Jani Nikula <jani.nikula@linux.intel.com> > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- > drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++++---------- > drivers/gpu/drm/i915/intel_device_info.c | 4 +- > 3 files changed, 32 insertions(+), 33 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index c9ba7d7f3787..d687c9503025 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3458,14 +3458,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, > * (DFLEXDPSP.DPX4TXLATC) > * > * This was done before tgl_ddi_pre_enable_dp by > - * haswell_crtc_enable()->intel_encoders_pre_pll_enable(). > + * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). > */ > > /* > * 4. Enable the port PLL. > * > * The PLL enabling itself was already done before this function by > - * haswell_crtc_enable()->intel_enable_shared_dpll(). We need only > + * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only > * configure the PLL to port mapping here. > */ > intel_ddi_clk_select(encoder, crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 5d43024f35aa..14726a293171 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -158,7 +158,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta > const struct intel_link_m_n *m2_n2); > static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); > static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state); > -static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state); > +static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state); > static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); > static void vlv_prepare_pll(struct intel_crtc *crtc, > const struct intel_crtc_state *pipe_config); > @@ -6787,8 +6787,8 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) > I915_WRITE(reg, val); > } > > -static void haswell_crtc_enable(struct intel_atomic_state *state, > - struct intel_crtc *crtc) > +static void hsw_crtc_enable(struct intel_atomic_state *state, > + struct intel_crtc *crtc) > { > const struct intel_crtc_state *new_crtc_state = > intel_atomic_get_new_crtc_state(state, crtc); > @@ -6829,7 +6829,7 @@ static void haswell_crtc_enable(struct intel_atomic_state *state, > > if (!transcoder_is_dsi(cpu_transcoder)) { > hsw_set_frame_start_delay(new_crtc_state); > - haswell_set_pipeconf(new_crtc_state); > + hsw_set_pipeconf(new_crtc_state); > } > > if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) > @@ -6967,8 +6967,8 @@ static void ironlake_crtc_disable(struct intel_atomic_state *state, > intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); > } > > -static void haswell_crtc_disable(struct intel_atomic_state *state, > - struct intel_crtc *crtc) > +static void hsw_crtc_disable(struct intel_atomic_state *state, > + struct intel_crtc *crtc) > { > /* > * FIXME collapse everything to one hook. > @@ -9783,7 +9783,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state) > POSTING_READ(PIPECONF(pipe)); > } > > -static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state) > +static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > @@ -10417,8 +10417,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, > > return ret; > } > -static int haswell_crtc_compute_clock(struct intel_crtc *crtc, > - struct intel_crtc_state *crtc_state) > + > +static int hsw_crtc_compute_clock(struct intel_crtc *crtc, > + struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct intel_atomic_state *state = > @@ -10532,9 +10533,8 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, > pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); > } > > -static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, > - enum port port, > - struct intel_crtc_state *pipe_config) > +static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, > + struct intel_crtc_state *pipe_config) > { > enum intel_dpll_id id; > u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); > @@ -10722,8 +10722,8 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, > return transcoder_is_dsi(pipe_config->cpu_transcoder); > } > > -static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > - struct intel_crtc_state *pipe_config) > +static void hsw_get_ddi_port_state(struct intel_crtc *crtc, > + struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; > @@ -10751,7 +10751,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > else if (IS_GEN9_LP(dev_priv)) > bxt_get_ddi_pll(dev_priv, port, pipe_config); > else > - haswell_get_ddi_pll(dev_priv, port, pipe_config); > + hsw_get_ddi_pll(dev_priv, port, pipe_config); > > pll = pipe_config->shared_dpll; > if (pll) { > @@ -10829,8 +10829,8 @@ static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_sta > crtc_state->sync_mode_slaves_mask); > } > > -static bool haswell_get_pipe_config(struct intel_crtc *crtc, > - struct intel_crtc_state *pipe_config) > +static bool hsw_get_pipe_config(struct intel_crtc *crtc, > + struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf; > @@ -10865,7 +10865,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > > if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || > INTEL_GEN(dev_priv) >= 11) { > - haswell_get_ddi_port_state(crtc, pipe_config); > + hsw_get_ddi_port_state(crtc, pipe_config); > intel_get_pipe_timings(crtc, pipe_config); > } > > @@ -14048,7 +14048,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state) > * multiple pipes, and planes are enabled after the pipe, we need to wait at > * least 2 vblanks on the first pipe before enabling planes on the second pipe. > */ > -static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state) > +static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) > { > struct intel_crtc_state *crtc_state; > struct intel_crtc *crtc; > @@ -14143,7 +14143,7 @@ static int intel_modeset_checks(struct intel_atomic_state *state) > intel_modeset_clear_plls(state); > > if (IS_HASWELL(dev_priv)) > - return haswell_mode_set_planes_workaround(state); > + return hsw_mode_set_planes_workaround(state); > > return 0; > } > @@ -16814,21 +16814,20 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) > intel_init_cdclk_hooks(dev_priv); > > if (INTEL_GEN(dev_priv) >= 9) { > - dev_priv->display.get_pipe_config = haswell_get_pipe_config; > + dev_priv->display.get_pipe_config = hsw_get_pipe_config; > dev_priv->display.get_initial_plane_config = > skylake_get_initial_plane_config; > - dev_priv->display.crtc_compute_clock = > - haswell_crtc_compute_clock; > - dev_priv->display.crtc_enable = haswell_crtc_enable; > - dev_priv->display.crtc_disable = haswell_crtc_disable; > + dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; > + dev_priv->display.crtc_enable = hsw_crtc_enable; > + dev_priv->display.crtc_disable = hsw_crtc_disable; > } else if (HAS_DDI(dev_priv)) { > - dev_priv->display.get_pipe_config = haswell_get_pipe_config; > + dev_priv->display.get_pipe_config = hsw_get_pipe_config; > dev_priv->display.get_initial_plane_config = > i9xx_get_initial_plane_config; > dev_priv->display.crtc_compute_clock = > - haswell_crtc_compute_clock; > - dev_priv->display.crtc_enable = haswell_crtc_enable; > - dev_priv->display.crtc_disable = haswell_crtc_disable; > + hsw_crtc_compute_clock; > + dev_priv->display.crtc_enable = hsw_crtc_enable; > + dev_priv->display.crtc_disable = hsw_crtc_disable; > } else if (HAS_PCH_SPLIT(dev_priv)) { > dev_priv->display.get_pipe_config = ironlake_get_pipe_config; > dev_priv->display.get_initial_plane_config = > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 1acb5db77431..ca7a42e1d769 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -600,7 +600,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) > sseu->has_eu_pg = 0; > } > > -static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) > +static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) > { > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > u32 fuse1; > @@ -1021,7 +1021,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > > /* Initialize slice/subslice/EU info */ > if (IS_HASWELL(dev_priv)) > - haswell_sseu_info_init(dev_priv); > + hsw_sseu_info_init(dev_priv); > else if (IS_CHERRYVIEW(dev_priv)) > cherryview_sseu_info_init(dev_priv); > else if (IS_BROADWELL(dev_priv)) > -- > 2.24.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index c9ba7d7f3787..d687c9503025 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3458,14 +3458,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, * (DFLEXDPSP.DPX4TXLATC) * * This was done before tgl_ddi_pre_enable_dp by - * haswell_crtc_enable()->intel_encoders_pre_pll_enable(). + * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). */ /* * 4. Enable the port PLL. * * The PLL enabling itself was already done before this function by - * haswell_crtc_enable()->intel_enable_shared_dpll(). We need only + * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only * configure the PLL to port mapping here. */ intel_ddi_clk_select(encoder, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5d43024f35aa..14726a293171 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -158,7 +158,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta const struct intel_link_m_n *m2_n2); static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state); -static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state); +static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state); static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); static void vlv_prepare_pll(struct intel_crtc *crtc, const struct intel_crtc_state *pipe_config); @@ -6787,8 +6787,8 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) I915_WRITE(reg, val); } -static void haswell_crtc_enable(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static void hsw_crtc_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) { const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -6829,7 +6829,7 @@ static void haswell_crtc_enable(struct intel_atomic_state *state, if (!transcoder_is_dsi(cpu_transcoder)) { hsw_set_frame_start_delay(new_crtc_state); - haswell_set_pipeconf(new_crtc_state); + hsw_set_pipeconf(new_crtc_state); } if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) @@ -6967,8 +6967,8 @@ static void ironlake_crtc_disable(struct intel_atomic_state *state, intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); } -static void haswell_crtc_disable(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static void hsw_crtc_disable(struct intel_atomic_state *state, + struct intel_crtc *crtc) { /* * FIXME collapse everything to one hook. @@ -9783,7 +9783,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state) POSTING_READ(PIPECONF(pipe)); } -static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state) +static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -10417,8 +10417,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, return ret; } -static int haswell_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) + +static int hsw_crtc_compute_clock(struct intel_crtc *crtc, + struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_atomic_state *state = @@ -10532,9 +10533,8 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); } -static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, - enum port port, - struct intel_crtc_state *pipe_config) +static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, + struct intel_crtc_state *pipe_config) { enum intel_dpll_id id; u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); @@ -10722,8 +10722,8 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, return transcoder_is_dsi(pipe_config->cpu_transcoder); } -static void haswell_get_ddi_port_state(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +static void hsw_get_ddi_port_state(struct intel_crtc *crtc, + struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; @@ -10751,7 +10751,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, else if (IS_GEN9_LP(dev_priv)) bxt_get_ddi_pll(dev_priv, port, pipe_config); else - haswell_get_ddi_pll(dev_priv, port, pipe_config); + hsw_get_ddi_pll(dev_priv, port, pipe_config); pll = pipe_config->shared_dpll; if (pll) { @@ -10829,8 +10829,8 @@ static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_sta crtc_state->sync_mode_slaves_mask); } -static bool haswell_get_pipe_config(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +static bool hsw_get_pipe_config(struct intel_crtc *crtc, + struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf; @@ -10865,7 +10865,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || INTEL_GEN(dev_priv) >= 11) { - haswell_get_ddi_port_state(crtc, pipe_config); + hsw_get_ddi_port_state(crtc, pipe_config); intel_get_pipe_timings(crtc, pipe_config); } @@ -14048,7 +14048,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state) * multiple pipes, and planes are enabled after the pipe, we need to wait at * least 2 vblanks on the first pipe before enabling planes on the second pipe. */ -static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state) +static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) { struct intel_crtc_state *crtc_state; struct intel_crtc *crtc; @@ -14143,7 +14143,7 @@ static int intel_modeset_checks(struct intel_atomic_state *state) intel_modeset_clear_plls(state); if (IS_HASWELL(dev_priv)) - return haswell_mode_set_planes_workaround(state); + return hsw_mode_set_planes_workaround(state); return 0; } @@ -16814,21 +16814,20 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) intel_init_cdclk_hooks(dev_priv); if (INTEL_GEN(dev_priv) >= 9) { - dev_priv->display.get_pipe_config = haswell_get_pipe_config; + dev_priv->display.get_pipe_config = hsw_get_pipe_config; dev_priv->display.get_initial_plane_config = skylake_get_initial_plane_config; - dev_priv->display.crtc_compute_clock = - haswell_crtc_compute_clock; - dev_priv->display.crtc_enable = haswell_crtc_enable; - dev_priv->display.crtc_disable = haswell_crtc_disable; + dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; + dev_priv->display.crtc_enable = hsw_crtc_enable; + dev_priv->display.crtc_disable = hsw_crtc_disable; } else if (HAS_DDI(dev_priv)) { - dev_priv->display.get_pipe_config = haswell_get_pipe_config; + dev_priv->display.get_pipe_config = hsw_get_pipe_config; dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config; dev_priv->display.crtc_compute_clock = - haswell_crtc_compute_clock; - dev_priv->display.crtc_enable = haswell_crtc_enable; - dev_priv->display.crtc_disable = haswell_crtc_disable; + hsw_crtc_compute_clock; + dev_priv->display.crtc_enable = hsw_crtc_enable; + dev_priv->display.crtc_disable = hsw_crtc_disable; } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv->display.get_pipe_config = ironlake_get_pipe_config; dev_priv->display.get_initial_plane_config = diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 1acb5db77431..ca7a42e1d769 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -600,7 +600,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) sseu->has_eu_pg = 0; } -static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) +static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) { struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; u32 fuse1; @@ -1021,7 +1021,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) /* Initialize slice/subslice/EU info */ if (IS_HASWELL(dev_priv)) - haswell_sseu_info_init(dev_priv); + hsw_sseu_info_init(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) cherryview_sseu_info_init(dev_priv); else if (IS_BROADWELL(dev_priv))