diff mbox series

[5.10.y-cip,19/27] arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash

Message ID 20220131121903.8620-20-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add RPCIF, SCI{F1} support to Renesas RZ/G2L SoC | expand

Commit Message

Lad Prabhakar Jan. 31, 2022, 12:18 p.m. UTC 
commit c81bd70f47cef36f88074d119e6e49cf92707fdb upstream.

Enable mt25qu512a flash connected to QSPI0.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211121234906.9602-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied the changes.]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../boot/dts/renesas/rzg2l-smarc-som.dtsi     | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

Comments

Pavel Machek Feb. 1, 2022, 11:10 a.m. UTC | #1 
Hi!

> commit c81bd70f47cef36f88074d119e6e49cf92707fdb upstream.
> 
> Enable mt25qu512a flash connected to QSPI0.
> 

> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			boot@0 {
> +				reg = <0x00000000 0x2000000>;
> +				read-only;
> +			};
> +			user@2000000 {
> +				reg = <0x2000000 0x2000000>;
> +			};

This confused me for a while. Some of hex numbers are 7 digits, some
are 8. Making it consistent at 8 digits would be good. (Or maybe 
using 0x0 so it is clear we are not aiming for 8 digits).

Best regards,
								Pavel
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 1fd961066236..9804ca0fd528 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -129,4 +129,44 @@ 
 			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
 			 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
 	};
+
+	qspi0_pins: qspi0 {
+		qspi0-data {
+			pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
+			power-source = <1800>;
+		};
+
+		qspi0-ctrl {
+			pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
+			power-source = <1800>;
+		};
+	};
+};
+
+&sbc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "micron,mt25qu512a", "jedec,spi-nor";
+		reg = <0>;
+		m25p,fast-read;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			boot@0 {
+				reg = <0x00000000 0x2000000>;
+				read-only;
+			};
+			user@2000000 {
+				reg = <0x2000000 0x2000000>;
+			};
+		};
+	};
 };