Message ID | 20220131121903.8620-28-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | Add RPCIF, SCI{F1} support to Renesas RZ/G2L SoC | expand |
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 7efe2e86b417..ebe155ccd721 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -28,11 +28,6 @@ clock-frequency = <0>; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -71,6 +66,11 @@ }; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>;