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[v2,5.10.y-cip,24/44] dt-bindings: riscv: Sort the CPU core list alphabetically

Message ID 20240206122734.13477-25-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add support for Renesas RZ/Five RISC-V SoC | expand

Commit Message

Lad Prabhakar Feb. 6, 2024, 12:27 p.m. UTC 
commit 57e1b873c2f54253f4c81bddb782e183ee6544ae upstream.

Sort the CPU cores list alphabetically for maintenance.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: dropped unsupported SoCs]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0b16e46..cd218c8e21042 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,12 +27,12 @@  properties:
     oneOf:
       - items:
           - enum:
-              - sifive,rocket0
               - sifive,e5
               - sifive,e51
-              - sifive,u54-mc
-              - sifive,u54
+              - sifive,rocket0
               - sifive,u5
+              - sifive,u54
+              - sifive,u54-mc
           - const: riscv
       - const: riscv    # Simulator only
     description: