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[v2,5.10.y-cip,06/44] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()

Message ID 20240206122734.13477-7-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add support for Renesas RZ/Five RISC-V SoC | expand

Commit Message

Lad Prabhakar Feb. 6, 2024, 12:26 p.m. UTC
From: Xiongfeng Wang <wangxiongfeng2@huawei.com>

commit e022eac85ecd2140a0829970d923d984356185eb upstream.

On ARM64, when PPTT(Processor Properties Topology Table) is not
implemented in ACPI boot, we will goto 'free_ci' with the following
  Unable to detect cache hierarchy for CPU 0

But some other codes may still use 'num_leaves' to iterate through the
'info_list', such as get_cpu_cacheinfo_id(). If 'info_list' is NULL , it
would crash. So clear 'num_leaves' in free_cache_attributes().

Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Link: https://lore.kernel.org/r/1626226375-58730-1-git-send-email-wangxiongfeng2@huawei.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
 drivers/base/cacheinfo.c | 1 +
 1 file changed, 1 insertion(+)
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diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index bfc095956dd11..dad2962291614 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -297,6 +297,7 @@  static void free_cache_attributes(unsigned int cpu)
 	per_cpu_cacheinfo(cpu) = NULL;
+	cache_leaves(cpu) = 0;
 int __weak init_cache_level(unsigned int cpu)