[v2,5.10.y-cip,42/44] riscv: dts: renesas: r9a07g043f: Add L2 cache node

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH v2 5.10.y-cip 42/44] riscv: dts: renesas: r9a07g043f: Add L2
 cache node
Date: Tue,  6 Feb 2024 12:27:32 +0000
Message-Id: <20240206122734.13477-43-prabhakar.mahadev-lad.rj@bp.renesas.com>
In-Reply-To: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Message ID	20240206122734.13477-43-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State	New
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com> Subject: [PATCH v2 5.10.y-cip 42/44] riscv: dts: renesas: r9a07g043f: Add L2 cache node Date: Tue, 6 Feb 2024 12:27:32 +0000 Message-Id: <20240206122734.13477-43-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add support for Renesas RZ/Five RISC-V SoC \| expand [v2,5.10.y-cip,00/44] Add support for Renesas RZ/Five RISC-V SoC [v2,5.10.y-cip,01/44] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS [v2,5.10.y-cip,02/44] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS [v2,5.10.y-cip,03/44] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to speci… [v2,5.10.y-cip,04/44] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels [v2,5.10.y-cip,05/44] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts [v2,5.10.y-cip,06/44] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() [v2,5.10.y-cip,07/44] riscv: Kconfig: Enable cpufreq kconfig menu [v2,5.10.y-cip,08/44] dma-direct: add support for dma_coherent_default_memory [v2,5.10.y-cip,09/44] dma-mapping: allow using the global coherent pool for !ARM [v2,5.10.y-cip,10/44] dma-mapping: simplify dma_init_coherent_memory [v2,5.10.y-cip,11/44] dma-mapping: add a dma_init_global_coherent helper [v2,5.10.y-cip,12/44] dma-mapping: make the global coherent pool conditional [v2,5.10.y-cip,13/44] of: also handle dma-noncoherent in of_dma_is_coherent() [v2,5.10.y-cip,14/44] of/irq: Use interrupts-extended to find parent [v2,5.10.y-cip,15/44] irqchip/sifive-plic: Improve naming scheme for per context offsets [v2,5.10.y-cip,16/44] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode [v2,5.10.y-cip,17/44] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC [v2,5.10.y-cip,18/44] irqchip/sifive-plic: Make better use of the effective affinity mask [v2,5.10.y-cip,19/44] irqchip/sifive-plic: Separate the enable and mask operations [v2,5.10.y-cip,20/44] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC [v2,5.10.y-cip,21/44] clocksource/drivers/riscv: Increase the clock source rating [v2,5.10.y-cip,22/44] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback [v2,5.10.y-cip,23/44] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on AR… [v2,5.10.y-cip,24/44] dt-bindings: riscv: Sort the CPU core list alphabetically [v2,5.10.y-cip,25/44] dt-bindings: riscv: Add Andes AX45MP core to the list [v2,5.10.y-cip,26/44] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset De… [v2,5.10.y-cip,27/44] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for … [v2,5.10.y-cip,28/44] soc: renesas: Identify RZ/Five SoC [v2,5.10.y-cip,29/44] clk: renesas: r9a07g043: Add support for RZ/Five SoC [v2,5.10.y-cip,30/44] cache: Add L2 cache management for Andes AX45MP RISC-V core [v2,5.10.y-cip,31/44] cache: ax45mp_cache: Add non coherent support [v2,5.10.y-cip,32/44] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC [v2,5.10.y-cip,33/44] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option [v2,5.10.y-cip,34/44] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC [v2,5.10.y-cip,35/44] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK [v2,5.10.y-cip,36/44] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zone… [v2,5.10.y-cip,37/44] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C [v2,5.10.y-cip,38/44] riscv: dts: renesas: rzfive-smarc-som: Enable WDT [v2,5.10.y-cip,39/44] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes [v2,5.10.y-cip,40/44] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} [v2,5.10.y-cip,41/44] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node [v2,5.10.y-cip,42/44] riscv: dts: renesas: r9a07g043f: Add L2 cache node [v2,5.10.y-cip,43/44] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property [v2,5.10.y-cip,44/44] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly di…

[v2,5.10.y-cip,42/44] riscv: dts: renesas: r9a07g043f: Add L2 cache node

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Patch