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[v8,0/7] Implement CMRR Support

Message ID 20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com (mailing list archive)
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Series Implement CMRR Support | expand

Message

Golani, Mitulkumar Ajitkumar May 9, 2024, 7:58 a.m. UTC
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.

enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.

--v6:
- CMRR handling in co-existatnce of LRR and DRRS
- Correct vtotal paramas accuracy and add 2 digit precision.

--v7:
- Rebased patches in-accordance to AS SDP merge.
- Add neccessary gaurd to prevent crtc_state mismatch
during intel_vrr_get_config.

-v8:
- Add support for AS SDP for CMRR.
- update palce holder for CMRR register(Jani).
- Make CMRR as subset of FAVT, as per comments in patch#3.

Mitul Golani (7):
  drm/i915: Define and compute Transcoder CMRR registers
  drm/i915: Add Enable/Disable for CMRR based on VRR state
  drm/i915: Compute CMRR and calculate vtotal
  Add refresh rate divider to struct representing AS SDP
  drm/i915/display: Add support for pack and unpack
  drm/i915/display: Compute Adaptive sync SDP params
  drm/i915/display: Compute vrr vsync params

 drivers/gpu/drm/i915/display/intel_display.c  |  61 ++++++-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  20 ++-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 168 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h               |  10 ++
 include/drm/display/drm_dp_helper.h           |   1 +
 7 files changed, 230 insertions(+), 37 deletions(-)