| Message ID | 20240509075833.1858363-5-mitulkumar.ajitkumar.golani@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Implement CMRR Support | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mitul > Golani > Sent: Thursday, May 9, 2024 1:29 PM > To: intel-gfx@lists.freedesktop.org > Cc: Shankar, Uma <uma.shankar@intel.com>; Nikula, Jani > <jani.nikula@intel.com> > Subject: [PATCH v8 4/7] Add refresh rate divider to struct representing AS SDP > > Add target_rr_divider to structure representing AS SDP. > It is valid only in FAVT mode, sink device ignores the bit in AVT mode. > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > --- Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy -------------------- > include/drm/display/drm_dp_helper.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/drm/display/drm_dp_helper.h > b/include/drm/display/drm_dp_helper.h > index 8bed890eec2c..393dbf8cf6ab 100644 > --- a/include/drm/display/drm_dp_helper.h > +++ b/include/drm/display/drm_dp_helper.h > @@ -122,6 +122,7 @@ struct drm_dp_as_sdp { > int target_rr; > int duration_incr_ms; > int duration_decr_ms; > + bool target_rr_divider; > enum operation_mode mode; > }; > > -- > 2.25.1
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index 8bed890eec2c..393dbf8cf6ab 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -122,6 +122,7 @@ struct drm_dp_as_sdp { int target_rr; int duration_incr_ms; int duration_decr_ms; + bool target_rr_divider; enum operation_mode mode; };
Add target_rr_divider to structure representing AS SDP. It is valid only in FAVT mode, sink device ignores the bit in AVT mode. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- include/drm/display/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+)