diff mbox series

[v8,7/7] drm/i915/display: Compute vrr vsync params

Message ID 20240509075833.1858363-8-mitulkumar.ajitkumar.golani@intel.com (mailing list archive)
State New
Headers show
Series Implement CMRR Support | expand

Commit Message

Golani, Mitulkumar Ajitkumar May 9, 2024, 7:58 a.m. UTC
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Nautiyal, Ankit K May 23, 2024, 11:38 a.m. UTC | #1
On 5/9/2024 1:28 PM, Mitul Golani wrote:
> Compute vrr vsync params in case of FAVT as well instead of
> only to AVT mode of operation.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index f5ba87fa00fe..3713e9b0829b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -239,6 +239,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   	}
>   
> +	if (intel_dp_as_sdp_supported(intel_dp)) {
> +		crtc_state->vrr.vsync_start =
> +			(crtc_state->hw.adjusted_mode.crtc_vtotal -
> +			 crtc_state->hw.adjusted_mode.vsync_start);
> +		crtc_state->vrr.vsync_end =
> +			(crtc_state->hw.adjusted_mode.crtc_vtotal -
> +			 crtc_state->hw.adjusted_mode.vsync_end);
> +	}
> +

These lines are duplicated earlier in the: if 
(crtc_state->uapi.vrr_enabled)  block.

So lets remove from there.

Also I think need to re-organize the series so as to have the patch that 
sets cmrr.enable as true is the last one.

Regards,

Ankit


>   	/*
>   	 * For XE_LPD+, we use guardband and pipeline override
>   	 * is deprecated.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index f5ba87fa00fe..3713e9b0829b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -239,6 +239,15 @@  intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 	}
 
+	if (intel_dp_as_sdp_supported(intel_dp)) {
+		crtc_state->vrr.vsync_start =
+			(crtc_state->hw.adjusted_mode.crtc_vtotal -
+			 crtc_state->hw.adjusted_mode.vsync_start);
+		crtc_state->vrr.vsync_end =
+			(crtc_state->hw.adjusted_mode.crtc_vtotal -
+			 crtc_state->hw.adjusted_mode.vsync_end);
+	}
+
 	/*
 	 * For XE_LPD+, we use guardband and pipeline override
 	 * is deprecated.