Show patches with: Submitter = Zanoni, Paulo R       |    State = Action Required       |   584 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[18/24] drm/i915/icl: implement icl_digital_port_connected() - 1 - --- 2018-05-22 Zanoni, Paulo R New
[17/24] drm/i915/icl: Add 10-bit support for hdmi - 1 - --- 2018-05-22 Zanoni, Paulo R New
[16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT - 1 - --- 2018-05-22 Zanoni, Paulo R New
[15/24] drm/i915/icl: compute the TBT PLL registers - - - --- 2018-05-22 Zanoni, Paulo R New
[14/24] drm/i915/icl: start adding the TBT pll - 1 - --- 2018-05-22 Zanoni, Paulo R New
[13/24] drm/i915/icl: unconditionally init DDI for every port - 1 - --- 2018-05-22 Zanoni, Paulo R New
[12/24] drm/i915/icl: Calculate link clock using the new registers - 1 - --- 2018-05-22 Zanoni, Paulo R New
[11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs. - 1 - --- 2018-05-22 Zanoni, Paulo R New
[10/24] drm/i915/icl: add icelake_get_ddi_pll() - 1 - --- 2018-05-22 Zanoni, Paulo R New
[09/24] drm/i915/icl: Add Icelake PCH detection - 1 - --- 2018-05-22 Zanoni, Paulo R New
[08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin - 1 - --- 2018-05-22 Zanoni, Paulo R New
[07/24] drm/i915/icl: Add DDI HDMI level selection for ICL - 1 - --- 2018-05-22 Zanoni, Paulo R New
[06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE - 1 - --- 2018-05-22 Zanoni, Paulo R New
[05/24] drm/i915/icp: Add Interrupt Support - - - --- 2018-05-22 Zanoni, Paulo R New
[04/24] drm/i915/icl: Support for TC North Display interrupts - 1 - --- 2018-05-22 Zanoni, Paulo R New
[03/24] drm/i915/icl: introduce tc_port - 1 - --- 2018-05-22 Zanoni, Paulo R New
[02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC - - - --- 2018-05-22 Zanoni, Paulo R New
[01/24] drm/i915/icl: Extend AUX F interrupts to ICL - 1 - --- 2018-05-22 Zanoni, Paulo R New
[2/2] drm/i915: use the ICL stolen memory - 1 - --- 2018-05-04 Zanoni, Paulo R New
[1/2] x86/gpu: reserve ICL's graphics stolen memory 1 1 - --- 2018-05-04 Zanoni, Paulo R New
drm/i915/icl, x86/gpu: implement ICL stolen memory support - 1 - --- 2018-05-03 Zanoni, Paulo R New
[CI] drm/i915/icl: Add configuring MOCS in new Icelake engines - 1 - --- 2018-05-02 Zanoni, Paulo R New
drm/i915: enable the pipe/transcoder/planes later on HSW+ - 2 - --- 2018-05-02 Zanoni, Paulo R New
[3/8] drm/i915/icl: add basic support for the ICL clocks - 1 - --- 2018-04-27 Zanoni, Paulo R New
drm/i915: configure the transcoder clocks before touching pipeconf on HSW+ - - - --- 2018-04-27 Zanoni, Paulo R New
[libdrm] intel: add support for ICL 11 - 1 - --- 2018-04-26 Zanoni, Paulo R New
[8/8] drm/i915/icl: Fix the DP Max Voltage for ICL - 1 - --- 2018-03-28 Zanoni, Paulo R New
[7/8] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI - - - --- 2018-03-28 Zanoni, Paulo R New
[6/8] drm/i915/icl: compute the MG PLL registers - - - --- 2018-03-28 Zanoni, Paulo R New
[5/8] drm/i915/icl: compute the combo PHY (DPLL) DP registers - 1 - --- 2018-03-28 Zanoni, Paulo R New
[4/8] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers - 1 - --- 2018-03-28 Zanoni, Paulo R New
[3/8] drm/i915/icl: add basic support for the ICL clocks - - - --- 2018-03-28 Zanoni, Paulo R New
[2/8] drm/i915/icl: add definitions for the ICL PLL registers - 1 - --- 2018-03-28 Zanoni, Paulo R New
[1/8] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL - 1 - --- 2018-03-28 Zanoni, Paulo R New
drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER - 1 - --- 2018-03-23 Zanoni, Paulo R New
[7/7] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL - 1 - --- 2018-03-23 Zanoni, Paulo R New
[6/7] drm/i915/icl: Added 5k source scaling support for Gen11 platform - 1 - --- 2018-03-23 Zanoni, Paulo R New
[5/7] drm/i915/icl: HPD pin for port F - 1 - --- 2018-03-23 Zanoni, Paulo R New
[4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer - 1 - --- 2018-03-23 Zanoni, Paulo R New
[3/7] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI - 1 - --- 2018-03-23 Zanoni, Paulo R New
[2/7] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake. - 1 - --- 2018-03-23 Zanoni, Paulo R New
[1/7] drm/i915/icl: Add register definitions for Combo PHY vswing sequences. - 1 - --- 2018-03-23 Zanoni, Paulo R New
[08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI - 1 - --- 2018-03-23 Zanoni, Paulo R New
[02/17] drm/i915/icl: add basic support for the ICL clocks - - - --- 2018-03-23 Zanoni, Paulo R New
[01/17] drm/i915/icl: add definitions for the ICL PLL registers - - - --- 2018-03-23 Zanoni, Paulo R New
[17/17] drm/i915/icl: Fix the DP Max Voltage for ICL - 2 - --- 2018-02-22 Zanoni, Paulo R New
[16/17] drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes - - - --- 2018-02-22 Zanoni, Paulo R New
[15/17] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL - - - --- 2018-02-22 Zanoni, Paulo R New
[14/17] drm/i915/icl: Calculate link clock using the new registers - 1 - --- 2018-02-22 Zanoni, Paulo R New
[13/17] drm/i915/icl: Added 5k source scaling support for Gen11 platform - - - --- 2018-02-22 Zanoni, Paulo R New
[12/17] drm/i915/icl: HPD pin for port F - 1 - --- 2018-02-22 Zanoni, Paulo R New
[11/17] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI - - - --- 2018-02-22 Zanoni, Paulo R New
[10/17] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer - 1 - --- 2018-02-22 Zanoni, Paulo R New
[09/17] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI - - - --- 2018-02-22 Zanoni, Paulo R New
[08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI - 2 - --- 2018-02-22 Zanoni, Paulo R New
[07/17] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake. - 1 - --- 2018-02-22 Zanoni, Paulo R New
[06/17] drm/i915/icl: Add register definitions for Combo PHY vswing sequences. - 1 - --- 2018-02-22 Zanoni, Paulo R New
[05/17] drm/i915/icl: compute the MG PLL registers - - - --- 2018-02-22 Zanoni, Paulo R New
[04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers - 1 - --- 2018-02-22 Zanoni, Paulo R New
[03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers - 1 - --- 2018-02-22 Zanoni, Paulo R New
[02/17] drm/i915/icl: add basic support for the ICL clocks - 1 - --- 2018-02-22 Zanoni, Paulo R New
[01/17] drm/i915/icl: add definitions for the ICL PLL registers - - - --- 2018-02-22 Zanoni, Paulo R New
[2/6] drm/i915/icl: add the main CDCLK functions - 1 - --- 2018-02-06 Zanoni, Paulo R New
[6/6] drm/i915/icl: program mbus during pipe enable - 2 - --- 2018-02-05 Zanoni, Paulo R New
[6/6] drm/i915/icl: program mbus during pipe enable - 2 - --- 2018-02-05 Zanoni, Paulo R New
[5/6] drm/i915/icl: initialize MBus during display init - 2 - --- 2018-02-05 Zanoni, Paulo R New
[4/6] drm/i915/icl: Enable both DBuf slices during init - 1 - --- 2018-02-05 Zanoni, Paulo R New
[3/6] drm/i915/icl: implement the display init/uninit sequences - 1 - --- 2018-02-05 Zanoni, Paulo R New
[2/6] drm/i915/icl: add the main CDCLK functions - - - --- 2018-02-05 Zanoni, Paulo R New
[1/6] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values - 1 - --- 2018-02-05 Zanoni, Paulo R New
[01/17] drm/i915/icl: add the main CDCLK functions - - - --- 2018-02-02 Zanoni, Paulo R New
[02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values - 1 - --- 2018-02-02 Zanoni, Paulo R New
[9/9] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register - 1 1 --- 2018-01-30 Zanoni, Paulo R New
[8/9] drm/i915/icl: Set graphics mode register for gen11 - 1 - --- 2018-01-30 Zanoni, Paulo R New
[7/9] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field - 1 - --- 2018-01-30 Zanoni, Paulo R New
[6/9] drm/i915/gen11: fix the SAGV block time for gen11 - 2 - --- 2018-01-30 Zanoni, Paulo R New
[5/9] drm/i915/icl: Introduce MBus related registers - 2 - --- 2018-01-30 Zanoni, Paulo R New
[4/9] drm/i915/icl: NV12 y-plane ddb is not in same plane - 2 - --- 2018-01-30 Zanoni, Paulo R New
[3/9] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed - 1 - --- 2018-01-30 Zanoni, Paulo R New
[2/9] drm/i915/icl: Do not fix dbuf block size to 512 - 2 - --- 2018-01-30 Zanoni, Paulo R New
[1/9] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL - 2 - --- 2018-01-30 Zanoni, Paulo R New
[07/13] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed - 1 - --- 2018-01-29 Zanoni, Paulo R New
[06/17] drm/i915/icl: Do not fix dbuf block size to 512 - 2 - --- 2018-01-29 Zanoni, Paulo R New
[17/17] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field - 1 - --- 2018-01-23 Zanoni, Paulo R New
[16/17] drm/i915/icl: enable SAGV for ICL platform - 1 - --- 2018-01-23 Zanoni, Paulo R New
[15/17] drm/i915/gen11: fix the SAGV block time for gen11 - 2 - --- 2018-01-23 Zanoni, Paulo R New
[14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout - - - --- 2018-01-23 Zanoni, Paulo R New
[13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed - - - --- 2018-01-23 Zanoni, Paulo R New
[12/17] drm/i915/icl: track dbuf slice-2 status - 1 - --- 2018-01-23 Zanoni, Paulo R New
[11/17] drm/i915/icl: program mbus during pipe enable - 2 - --- 2018-01-23 Zanoni, Paulo R New
[10/17] drm/i915/icl: initialize MBus during display init - 2 - --- 2018-01-23 Zanoni, Paulo R New
[09/17] drm/i915/icl: Introduce MBus related registers - 2 - --- 2018-01-23 Zanoni, Paulo R New
[08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane - 2 - --- 2018-01-23 Zanoni, Paulo R New
[07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed - 2 - --- 2018-01-23 Zanoni, Paulo R New
[06/17] drm/i915/icl: Do not fix dbuf block size to 512 - - - --- 2018-01-23 Zanoni, Paulo R New
[05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL - 2 - --- 2018-01-23 Zanoni, Paulo R New
[04/17] drm/i915/icl: Enable both DBuf slices during init - - - --- 2018-01-23 Zanoni, Paulo R New
[03/17] drm/i915/icl: implement the display init/uninit sequences - 1 - --- 2018-01-23 Zanoni, Paulo R New
[02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values - 1 - --- 2018-01-23 Zanoni, Paulo R New
[01/17] drm/i915/icl: add the main CDCLK functions - - - --- 2018-01-23 Zanoni, Paulo R New
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