diff mbox series

[10/37] drm/i915: add pcie snoop flag

Message ID 20200521003803.18936-11-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Introduce DG1 | expand

Commit Message

Lucas De Marchi May 21, 2020, 12:37 a.m. UTC 
From: Matthew Auld <matthew.auld@intel.com>

Gen 12 dgfx devices are coherent with system memory even over PCIe.
Therefore supporting coherent userptr should be possible.

Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++-
 drivers/gpu/drm/i915/i915_drv.h             | 1 +
 drivers/gpu/drm/i915/i915_pci.c             | 3 ++-
 drivers/gpu/drm/i915/intel_device_info.h    | 1 +
 4 files changed, 6 insertions(+), 2 deletions(-)

Comments

Chris Wilson May 21, 2020, 8:15 a.m. UTC | #1 
Quoting Lucas De Marchi (2020-05-21 01:37:36)
> From: Matthew Auld <matthew.auld@intel.com>
> 
> Gen 12 dgfx devices are coherent with system memory even over PCIe.
> Therefore supporting coherent userptr should be possible.

Then set has-snoop with a comment that it is over PCIe. This patch only
covers one cache-coherent usecase, not all of them. Why not?
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 8b0708708671..0a375befd893 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -757,7 +757,8 @@  i915_gem_userptr_ioctl(struct drm_device *dev,
 	int ret;
 	u32 handle;
 
-	if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) {
+	if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv) &&
+	    !HAS_SNOOP_PCIE(dev_priv)) {
 		/* We cannot support coherent userptr objects on hw without
 		 * LLC and broken snooping.
 		 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 162b1ead88d3..a9846205a5e2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1566,6 +1566,7 @@  IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
 #define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
+#define HAS_SNOOP_PCIE(dev_priv)(INTEL_INFO(dev_priv)->has_snoop_pcie)
 #define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
 #define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7e3252fbad8e..be52d1b76b2e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -874,7 +874,8 @@  static const struct intel_device_info rkl_info = {
 
 #define GEN12_DGFX_FEATURES \
 	GEN12_FEATURES, \
-	.is_dgfx = 1
+	.is_dgfx = 1, \
+	.has_snoop_pcie = 1
 
 #undef GEN
 #undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ced979c9b366..4bcaa0d6a9e6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -128,6 +128,7 @@  enum intel_ppgtt_type {
 	func(has_rps); \
 	func(has_runtime_pm); \
 	func(has_snoop); \
+	func(has_snoop_pcie); \
 	func(has_coherent_ggtt); \
 	func(unfenced_needs_alignment); \
 	func(hws_needs_physical);