@@ -2659,6 +2659,19 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
}
+static int dg1_rawclk(struct drm_i915_private *i915)
+{
+ /*
+ * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
+ * "Program Numerator=2, Denominator=4, Divider=37 decimal."
+ */
+ intel_de_write(i915, PCH_RAWCLK_FREQ,
+ CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) |
+ ICP_RAWCLK_NUM(2));
+
+ return 38400;
+}
+
static int cnp_rawclk(struct drm_i915_private *dev_priv)
{
u32 rawclk;
@@ -2767,6 +2780,8 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
{
u32 freq;
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ freq = dg1_rawclk(dev_priv);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))