[01/20] drm/i915: Sort the mess around ICP TC hotplugs regs

Message ID	20201006143349.5561-2-ville.syrjala@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=f8CR=DN=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5DD0C204EF IronPort-SDR: /oa8BJHSc3m2sRMMlcz7MxzMTGJqH8AvAoJEUjO1MgUSXZp5sy9OrJ9WZ8AFzM17TNE9m/BofB RK2aqBrLHX0Q== IronPort-SDR: HaxCxXZrs74ig8wWXX50wC8aiK7Zq/ZJJEwffLVf9LAwAT1fWfYObnonUTvSWapVsWrLSSp4A5 37uRR0lE49Pw== From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:30 +0300 Message-Id: <20201006143349.5561-2-ville.syrjala@linux.intel.com> In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: Futher cleanup around hpd pins and port identfiers \| expand [00/20] drm/i915: Futher cleanup around hpd pins and port identfiers [01/20] drm/i915: Sort the mess around ICP TC hotplugs regs [02/20] drm/i915: s/PORT_TC/TC_PORT_TC/ [03/20] drm/i915: Add PORT_TCn aliases to enum port [04/20] drm/i915: Give DDI encoders even better names [05/20] drm/i915: Introduce AUX_CH_USBCn [06/20] drm/i915: Pimp AUX CH names [07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup [08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin [09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() [10/20] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits [11/20] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG() [12/20] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits [13/20] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs() [14/20] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants [15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall() [16/20] drm/i915: Rename 'tmp_mask' [17/20] drm/i915: Remove the per-plaform IIR HPD masking [18/20] drm/i915: Enable hpd logic only for ports that are present [19/20] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+ [20/20] drm/i915: Get rid of ibx_irq_pre_postinstall()

Message ID

20201006143349.5561-2-ville.syrjala@linux.intel.com (mailing list archive)

State

New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5DD0C204EF
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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Date: Tue,  6 Oct 2020 17:33:30 +0300
Message-Id: <20201006143349.5561-2-ville.syrjala@linux.intel.com>
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References: <20201006143349.5561-1-ville.syrjala@linux.intel.com>
MIME-Version: 1.0
Subject: [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC
 hotplugs regs
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Series

drm/i915: Futher cleanup around hpd pins and port identfiers | expand

Commit Message

Ville Syrjälä Oct. 6, 2020, 2:33 p.m. UTC

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move the DSC stuff out from the middle of the ICP HPD register
definitions. The location seems to have been selected by a
dice roll.

SHPD_FILTER_CNT addition also went astray due to the DSC
mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 215 ++++++++++++++++----------------
 1 file changed, 107 insertions(+), 108 deletions(-)

Comments

Lucas De Marchi Oct. 22, 2020, 11:22 p.m. UTC | #1

On Wed, Oct 07, 2020 at 03:11:56PM -0700, Lucas De Marchi wrote:
>On Tue, Oct 06, 2020 at 05:33:30PM +0300, Ville Syrjälä wrote:
>>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>>Move the DSC stuff out from the middle of the ICP HPD register
>>definitions. The location seems to have been selected by a
>>dice roll.
>>
>>SHPD_FILTER_CNT addition also went astray due to the DSC
>>mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT().
>>
>>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>---
>>drivers/gpu/drm/i915/i915_reg.h | 215 ++++++++++++++++----------------
>>1 file changed, 107 insertions(+), 108 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>index 6ad9ee4243a0..efe51a4ef719 100644
>>--- a/drivers/gpu/drm/i915/i915_reg.h
>>+++ b/drivers/gpu/drm/i915/i915_reg.h
>>@@ -4618,6 +4618,110 @@ enum {
>>#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME	REG_BIT(2)
>>#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE	REG_BIT(1)
>>
>>+/* Icelake DSC Rate Control Range Parameter Registers */
>>+#define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
>>+#define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
>>+#define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
>>+#define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>>+#define RC_BPG_OFFSET_SHIFT			10
>>+#define RC_MAX_QP_SHIFT				5
>>+#define RC_MIN_QP_SHIFT				0
>>+
>>+#define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
>>+#define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
>>+#define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
>>+#define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>>+
>>+#define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
>>+#define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
>>+#define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
>>+#define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>>+
>>+#define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
>>+#define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
>>+#define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
>>+#define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>>+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>>+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>>+
>>/* VGA port control */
>>#define ADPA			_MMIO(0x61100)
>>#define PCH_ADPA                _MMIO(0xe1100)
>>@@ -8305,117 +8409,12 @@ enum {
>>
>>#define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
>>#define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
>>-
>>-#define SHPD_FILTER_CNT				_MMIO(0xc4038)
>>-#define   SHPD_FILTER_CNT_500_ADJ		0x001D9
>>-
>>-/* Icelake DSC Rate Control Range Parameter Registers */
>>-#define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
>>-#define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
>>-#define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
>>-#define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>>-#define RC_BPG_OFFSET_SHIFT			10
>>-#define RC_MAX_QP_SHIFT				5
>>-#define RC_MIN_QP_SHIFT				0
>>-
>>-#define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
>>-#define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
>>-#define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
>>-#define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>>-
>>-#define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
>>-#define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
>>-#define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
>>-#define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>>-
>>-#define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
>>-#define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
>>-#define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
>>-#define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>>-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>>-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>>-
>>#define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
>>#define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
>>
>>+#define SHPD_FILTER_CNT				_MMIO(0xc4038)
>>+#define   SHPD_FILTER_CNT_500_ADJ		0x001D9
>>+
>
>that is a weird choice git 2.26 made for the diff, but looks correct. With
>--color-moved (and not sure if the version made any difference, but mine
>is 2.28) I could check this is plain move.
>
>Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>


Let's see if patchwork now accepts the comment without the email header
to ignore.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>


>
>Lucas De Marchi
>
>>#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
>>					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>>#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \
>>-- 
>>2.26.2
>>
>>_______________________________________________
>>Intel-gfx mailing list
>>Intel-gfx@lists.freedesktop.org
>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ad9ee4243a0..efe51a4ef719 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4618,6 +4618,110 @@  enum {
 #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME	REG_BIT(2)
 #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE	REG_BIT(1)
 
+/* Icelake DSC Rate Control Range Parameter Registers */
+#define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
+#define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
+#define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define RC_BPG_OFFSET_SHIFT			10
+#define RC_MAX_QP_SHIFT				5
+#define RC_MIN_QP_SHIFT				0
+
+#define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
+#define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
+#define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
+#define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
+#define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
+#define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
+#define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
+
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
 #define PCH_ADPA                _MMIO(0xe1100)
@@ -8305,117 +8409,12 @@  enum {
 
 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
 #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
-
-#define SHPD_FILTER_CNT				_MMIO(0xc4038)
-#define   SHPD_FILTER_CNT_500_ADJ		0x001D9
-
-/* Icelake DSC Rate Control Range Parameter Registers */
-#define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
-#define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
-#define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
-#define RC_BPG_OFFSET_SHIFT			10
-#define RC_MAX_QP_SHIFT				5
-#define RC_MIN_QP_SHIFT				0
-
-#define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
-#define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
-#define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
-
-#define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
-#define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
-#define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
-
-#define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
-#define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
-#define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
-
 #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
 
+#define SHPD_FILTER_CNT				_MMIO(0xc4038)
+#define   SHPD_FILTER_CNT_500_ADJ		0x001D9
+
 #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
 #define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \

[01/20] drm/i915: Sort the mess around ICP TC hotplugs regs

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