| Message ID | 20210515031035.2561658-17-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Alder Lake-P Support | expand |
On 2021-05-15 at 08:40:28 +0530, Matt Roper wrote: > From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > > It removes intel_crtc_state from function argument of > intel_psr_enable_source() in order to use intel_psr_enable_source() > without intel_crtc_state on other psr internal functions. > And we can get cpu_trancoder from intel_psr, therefore we don't need to > pass intel_crtc_state to this function. > > Cc: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 5bafd0de6ad9..cc85083dcd28 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -969,11 +969,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) > intel_dp->psr.active = true; > } > > -static void intel_psr_enable_source(struct intel_dp *intel_dp, > - const struct intel_crtc_state *crtc_state) > +static void intel_psr_enable_source(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; > u32 mask; > > /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ > @@ -1080,7 +1079,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, > &intel_dp->psr.vsc); > intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc); > intel_psr_enable_sink(intel_dp); > - intel_psr_enable_source(intel_dp, crtc_state); > + intel_psr_enable_source(intel_dp); > intel_dp->psr.enabled = true; > > intel_psr_activate(intel_dp); > -- > 2.25.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 5bafd0de6ad9..cc85083dcd28 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -969,11 +969,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) intel_dp->psr.active = true; } -static void intel_psr_enable_source(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static void intel_psr_enable_source(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 mask; /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ @@ -1080,7 +1079,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, &intel_dp->psr.vsc); intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc); intel_psr_enable_sink(intel_dp); - intel_psr_enable_source(intel_dp, crtc_state); + intel_psr_enable_source(intel_dp); intel_dp->psr.enabled = true; intel_psr_activate(intel_dp);