| Message ID | 20230606191504.18099-8-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Load LUTs with DSB | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Wednesday, June 7, 2023 12:45 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 07/19] drm/i915/dsb: Don't use indexed writes > when byte enables are not all set > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The indexed write instruction doesn't support byte-enables, so if the non- > indexed write used those we must not convert it to an indexed write. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> LGTM. Reviewed-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dsb.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c > b/drivers/gpu/drm/i915/display/intel_dsb.c > index a20ae5313d23..22c716ee75e2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -149,7 +149,7 @@ static bool intel_dsb_prev_ins_is_write(struct > intel_dsb *dsb, > if (dsb->free_pos == 0) > return false; > > - prev_opcode = buf[dsb->ins_start_offset + 1] >> > DSB_OPCODE_SHIFT; > + prev_opcode = buf[dsb->ins_start_offset + 1] & > ~DSB_REG_VALUE_MASK; > prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK; > > return prev_opcode == opcode && prev_reg == > i915_mmio_reg_offset(reg); @@ -157,12 +157,18 @@ static bool > intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, > > static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, > i915_reg_t reg) { > - return intel_dsb_prev_ins_is_write(dsb, > DSB_OPCODE_MMIO_WRITE, reg); > + /* only full byte-enables can be converted to indexed writes */ > + return intel_dsb_prev_ins_is_write(dsb, > + DSB_OPCODE_MMIO_WRITE << > DSB_OPCODE_SHIFT | > + DSB_BYTE_EN << > DSB_BYTE_EN_SHIFT, > + reg); > } > > static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, > i915_reg_t reg) { > - return intel_dsb_prev_ins_is_write(dsb, > DSB_OPCODE_INDEXED_WRITE, reg); > + return intel_dsb_prev_ins_is_write(dsb, > + DSB_OPCODE_INDEXED_WRITE << > DSB_OPCODE_SHIFT, > + reg); > } > > /** > -- > 2.39.3
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index a20ae5313d23..22c716ee75e2 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -149,7 +149,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, if (dsb->free_pos == 0) return false; - prev_opcode = buf[dsb->ins_start_offset + 1] >> DSB_OPCODE_SHIFT; + prev_opcode = buf[dsb->ins_start_offset + 1] & ~DSB_REG_VALUE_MASK; prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK; return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); @@ -157,12 +157,18 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg) { - return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_MMIO_WRITE, reg); + /* only full byte-enables can be converted to indexed writes */ + return intel_dsb_prev_ins_is_write(dsb, + DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT | + DSB_BYTE_EN << DSB_BYTE_EN_SHIFT, + reg); } static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) { - return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE, reg); + return intel_dsb_prev_ins_is_write(dsb, + DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT, + reg); } /**