diff mbox series

[v3,2/4] drm/i915/psr: Add alpm_parameters struct

Message ID 20240130111130.3298779-3-jouni.hogander@intel.com (mailing list archive)
State New, archived
Headers show
Series ALPM AUX Wake Configuration | expand

Commit Message

Hogander, Jouni Jan. 30, 2024, 11:11 a.m. UTC 
Add new alpm_parameters struct into intel_psr for all calculated
alpm parameters.

v2: Move alpm_parameters struct definition to intel_psr struct

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  8 ++++--
 drivers/gpu/drm/i915/display/intel_psr.c      | 28 ++++++++++---------
 2 files changed, 21 insertions(+), 15 deletions(-)

Comments

Arun R Murthy Feb. 6, 2024, 3:26 p.m. UTC | #1 
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Tuesday, January 30, 2024 4:41 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 2/4] drm/i915/psr: Add alpm_parameters struct
> 
> Add new alpm_parameters struct into intel_psr for all calculated alpm
> parameters.
> 
> v2: Move alpm_parameters struct definition to intel_psr struct
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>  .../drm/i915/display/intel_display_types.h    |  8 ++++--
>  drivers/gpu/drm/i915/display/intel_psr.c      | 28 ++++++++++---------
>  2 files changed, 21 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ae2e8cff9d69..ff6cd30b2b76 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1710,8 +1710,12 @@ struct intel_psr {
>  	bool psr2_sel_fetch_cff_enabled;
>  	bool req_psr2_sdp_prior_scanline;
>  	u8 sink_sync_latency;
> -	u8 io_wake_lines;
> -	u8 fast_wake_lines;
> +
> +	struct {
> +		u8 io_wake_lines;
> +		u8 fast_wake_lines;
> +	} alpm_parameters;
> +
>  	ktime_t last_entry_attempt;
>  	ktime_t last_exit;
>  	bool sink_not_reliable;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1010b8c405df..4bca1107997f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -779,8 +779,8 @@ static u32 intel_psr2_get_tp_time(struct intel_dp
> *intel_dp)
> 
>  static int psr2_block_count_lines(struct intel_dp *intel_dp)  {
> -	return intel_dp->psr.io_wake_lines < 9 &&
> -		intel_dp->psr.fast_wake_lines < 9 ? 8 : 12;
> +	return intel_dp->psr.alpm_parameters.io_wake_lines < 9 &&
> +		intel_dp->psr.alpm_parameters.fast_wake_lines < 9 ? 8 : 12;
>  }
> 
>  static int psr2_block_count(struct intel_dp *intel_dp) @@ -817,6 +817,7 @@
> static void dg2_activate_panel_replay(struct intel_dp *intel_dp)  static void
> hsw_activate_psr2(struct intel_dp *intel_dp)  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	struct intel_psr *psr = &intel_dp->psr;
>  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
>  	u32 val = EDP_PSR2_ENABLE;
>  	u32 psr_val = 0;
> @@ -858,17 +859,18 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>  		 */
>  		int tmp;
> 
> -		tmp = map[intel_dp->psr.io_wake_lines -
> TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
> +		tmp = map[psr->alpm_parameters.io_wake_lines -
> +			  TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
>  		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp +
> TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES);
> 
> -		tmp = map[intel_dp->psr.fast_wake_lines -
> TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
> +		tmp = map[psr->alpm_parameters.fast_wake_lines -
> +TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
>  		val |= TGL_EDP_PSR2_FAST_WAKE(tmp +
> TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
>  	} else if (DISPLAY_VER(dev_priv) >= 12) {
> -		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp-
> >psr.io_wake_lines);
> -		val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp-
> >psr.fast_wake_lines);
> +		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr-
> >alpm_parameters.io_wake_lines);
> +		val |= TGL_EDP_PSR2_FAST_WAKE(psr-
> >alpm_parameters.fast_wake_lines);
>  	} else if (DISPLAY_VER(dev_priv) >= 9) {
> -		val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp-
> >psr.io_wake_lines);
> -		val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
> +		val |= EDP_PSR2_IO_BUFFER_WAKE(psr-
> >alpm_parameters.io_wake_lines);
> +		val |= EDP_PSR2_FAST_WAKE(psr-
> >alpm_parameters.fast_wake_lines);
>  	}
> 
>  	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
> @@ -1124,8 +1126,8 @@ static bool
> _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
>  	return true;
>  }
> 
> -static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
> -				     struct intel_crtc_state *crtc_state)
> +static bool _compute_alpm_params(struct intel_dp *intel_dp,
> +				 struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; @@
> -1158,8 +1160,8 @@ static bool _compute_psr2_wake_times(struct intel_dp
> *intel_dp,
>  		io_wake_lines = fast_wake_lines = max_wake_lines;
> 
>  	/* According to Bspec lower limit should be set as 7 lines. */
> -	intel_dp->psr.io_wake_lines = max(io_wake_lines, 7);
> -	intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7);
> +	intel_dp->psr.alpm_parameters.io_wake_lines = max(io_wake_lines, 7);
> +	intel_dp->psr.alpm_parameters.fast_wake_lines = max(fast_wake_lines,
> +7);
> 
>  	return true;
>  }
> @@ -1291,7 +1293,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
>  		return false;
>  	}
> 
> -	if (!_compute_psr2_wake_times(intel_dp, crtc_state)) {
> +	if (!_compute_alpm_params(intel_dp, crtc_state)) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "PSR2 not enabled, Unable to use long enough wake
> times\n");
>  		return false;
> --
> 2.34.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ae2e8cff9d69..ff6cd30b2b76 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1710,8 +1710,12 @@  struct intel_psr {
 	bool psr2_sel_fetch_cff_enabled;
 	bool req_psr2_sdp_prior_scanline;
 	u8 sink_sync_latency;
-	u8 io_wake_lines;
-	u8 fast_wake_lines;
+
+	struct {
+		u8 io_wake_lines;
+		u8 fast_wake_lines;
+	} alpm_parameters;
+
 	ktime_t last_entry_attempt;
 	ktime_t last_exit;
 	bool sink_not_reliable;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1010b8c405df..4bca1107997f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -779,8 +779,8 @@  static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 
 static int psr2_block_count_lines(struct intel_dp *intel_dp)
 {
-	return intel_dp->psr.io_wake_lines < 9 &&
-		intel_dp->psr.fast_wake_lines < 9 ? 8 : 12;
+	return intel_dp->psr.alpm_parameters.io_wake_lines < 9 &&
+		intel_dp->psr.alpm_parameters.fast_wake_lines < 9 ? 8 : 12;
 }
 
 static int psr2_block_count(struct intel_dp *intel_dp)
@@ -817,6 +817,7 @@  static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_psr *psr = &intel_dp->psr;
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 	u32 val = EDP_PSR2_ENABLE;
 	u32 psr_val = 0;
@@ -858,17 +859,18 @@  static void hsw_activate_psr2(struct intel_dp *intel_dp)
 		 */
 		int tmp;
 
-		tmp = map[intel_dp->psr.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
+		tmp = map[psr->alpm_parameters.io_wake_lines -
+			  TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
 		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES);
 
-		tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
+		tmp = map[psr->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
 		val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
-		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
-		val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
+		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
+		val |= TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
 	} else if (DISPLAY_VER(dev_priv) >= 9) {
-		val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
-		val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
+		val |= EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
+		val |= EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
 	}
 
 	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
@@ -1124,8 +1126,8 @@  static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
 	return true;
 }
 
-static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
-				     struct intel_crtc_state *crtc_state)
+static bool _compute_alpm_params(struct intel_dp *intel_dp,
+				 struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
@@ -1158,8 +1160,8 @@  static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
 		io_wake_lines = fast_wake_lines = max_wake_lines;
 
 	/* According to Bspec lower limit should be set as 7 lines. */
-	intel_dp->psr.io_wake_lines = max(io_wake_lines, 7);
-	intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7);
+	intel_dp->psr.alpm_parameters.io_wake_lines = max(io_wake_lines, 7);
+	intel_dp->psr.alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);
 
 	return true;
 }
@@ -1291,7 +1293,7 @@  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!_compute_psr2_wake_times(intel_dp, crtc_state)) {
+	if (!_compute_alpm_params(intel_dp, crtc_state)) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR2 not enabled, Unable to use long enough wake times\n");
 		return false;