diff mbox series

[v3,4/4] drm/i915/alpm: Alpm aux wake configuration for lnl

Message ID 20240130111130.3298779-5-jouni.hogander@intel.com (mailing list archive)
State New, archived
Headers show
Series ALPM AUX Wake Configuration | expand

Commit Message

Hogander, Jouni Jan. 30, 2024, 11:11 a.m. UTC
Lunarlake has some configurations in ALPM_CTL register for legacy ALPM as
well. Write these.

Bspec: 71477

v2: move version check to lnl_alpm_configure

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Comments

Murthy, Arun R Feb. 6, 2024, 3:29 p.m. UTC | #1
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Tuesday, January 30, 2024 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 4/4] drm/i915/alpm: Alpm aux wake configuration for lnl
> 
> Lunarlake has some configurations in ALPM_CTL register for legacy ALPM as
> well. Write these.
> 
> Bspec: 71477
> 
> v2: move version check to lnl_alpm_configure
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>  drivers/gpu/drm/i915/display/intel_psr.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7aedda0ca2d2..72cadad09db5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1554,6 +1554,21 @@ static void wm_optimization_wa(struct intel_dp
> *intel_dp,
>  			     wa_16013835468_bit_get(intel_dp), 0);  }
> 
> +static void lnl_alpm_configure(struct intel_dp *intel_dp) {
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> +	struct intel_psr *psr = &intel_dp->psr;
> +
> +	if (DISPLAY_VER(dev_priv) < 20)
> +		return;
> +
> +	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder),
> +		       ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> +		       ALPM_CTL_ALPM_ENTRY_CHECK(psr-
> >alpm_parameters.check_entry_lines) |
> +
> +ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr-
> >alpm_parameters.fast_wake_lines))
> +;
> +}
> +
>  static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  				    const struct intel_crtc_state *crtc_state)  {
> @@ -1619,6 +1634,8 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  			     intel_dp->psr.psr2_sel_fetch_enabled ?
>  			     IGNORE_PSR2_HW_TRACKING : 0);
> 
> +	lnl_alpm_configure(intel_dp);
> +
>  	/*
>  	 * Wa_16013835468
>  	 * Wa_14015648006
> --
> 2.34.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7aedda0ca2d2..72cadad09db5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1554,6 +1554,21 @@  static void wm_optimization_wa(struct intel_dp *intel_dp,
 			     wa_16013835468_bit_get(intel_dp), 0);
 }
 
+static void lnl_alpm_configure(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+	struct intel_psr *psr = &intel_dp->psr;
+
+	if (DISPLAY_VER(dev_priv) < 20)
+		return;
+
+	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder),
+		       ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
+		       ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines) |
+		       ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines));
+}
+
 static void intel_psr_enable_source(struct intel_dp *intel_dp,
 				    const struct intel_crtc_state *crtc_state)
 {
@@ -1619,6 +1634,8 @@  static void intel_psr_enable_source(struct intel_dp *intel_dp,
 			     intel_dp->psr.psr2_sel_fetch_enabled ?
 			     IGNORE_PSR2_HW_TRACKING : 0);
 
+	lnl_alpm_configure(intel_dp);
+
 	/*
 	 * Wa_16013835468
 	 * Wa_14015648006