diff mbox series

[kvm-unit-tests,14/14] x86: msr: Verify that EFER.SCE can be written on 32-bit vCPUs

Message ID 20210422030504.3488253-15-seanjc@google.com (mailing list archive)
State New, archived
Headers show
Series x86: MSR_GS_BASE and friends | expand

Commit Message

Sean Christopherson April 22, 2021, 3:05 a.m. UTC 
Verify that EFER can be written, and that the SYSCALL enable bit can be
set, on 32-bit vCPUs.

Signed-off-by: Sean Christopherson <seanjc@google.com>
---
 x86/msr.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/x86/msr.c b/x86/msr.c
index 8a1b0b2..7a551c4 100644
--- a/x86/msr.c
+++ b/x86/msr.c
@@ -29,9 +29,7 @@  struct msr_info msr_info[] =
 	MSR_TEST(MSR_FS_BASE, addr_64, true),
 	MSR_TEST(MSR_GS_BASE, addr_64, true),
 	MSR_TEST(MSR_KERNEL_GS_BASE, addr_64, true),
-#ifdef __x86_64__
-	MSR_TEST(MSR_EFER, 0xD00, false),
-#endif
+	MSR_TEST(MSR_EFER, EFER_SCE, false),
 	MSR_TEST(MSR_LSTAR, addr_64, true),
 	MSR_TEST(MSR_CSTAR, addr_64, true),
 	MSR_TEST(MSR_SYSCALL_MASK, 0xffffffff, true),
@@ -44,6 +42,13 @@  static void test_msr_rw(struct msr_info *msr, unsigned long long val)
 	unsigned long long r, orig;
 
 	orig = rdmsr(msr->index);
+	/*
+	 * Special case EFER since clearing LME/LMA is not allowed in 64-bit mode,
+	 * and conversely setting those bits on 32-bit CPUs is not allowed.  Treat
+	 * the desired value as extra bits to set.
+	 */
+	if (msr->index == MSR_EFER)
+		val |= orig;
 	wrmsr(msr->index, val);
 	r = rdmsr(msr->index);
 	wrmsr(msr->index, orig);