diff mbox series

[v1,22/50] ARM: dts: exynos: OPPs for bus_disp1 in Exynos5420

Message ID 20190715124417.4787-23-l.luba@partner.samsung.com (mailing list archive)
State New, archived
Headers show
Series [v1,01/50] clk: samsung: add new IDs for Exynos5420 clocks | expand

Commit Message

Lukasz Luba July 15, 2019, 12:43 p.m. UTC 
Update the bus_disp1 OPPs and add 400MHz which is max frequency for this
bus. The frequencies are aligned to parent clock such that it is not
needed to change the PLL rate.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 2b36c2f77a10..6e82ffcbeacd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1305,7 +1305,7 @@ 
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <120000000>;
+				opp-hz = /bits/ 64 <150000000>;
 			};
 			opp01 {
 				opp-hz = /bits/ 64 <200000000>;
@@ -1313,6 +1313,9 @@ 
 			opp02 {
 				opp-hz = /bits/ 64 <300000000>;
 			};
+			opp03 {
+				opp-hz = /bits/ 64 <400000000>;
+			};
 		};
 
 		bus_gscl_opp_table: opp_table15 {