diff mbox series

[v1,24/50] ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420

Message ID 20190715124417.4787-25-l.luba@partner.samsung.com (mailing list archive)
State New, archived
Headers show
Series [v1,01/50] clk: samsung: add new IDs for Exynos5420 clocks | expand

Commit Message

Lukasz Luba July 15, 2019, 12:43 p.m. UTC 
The OPPs must reflect possible values after dividing the master clock.
The old values 400 and 333, 222, etc does not have common parent rate.
Thus, align the values to parent rate such that they will be set exactly
using only a divider.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0739e7bd4628..74d014f3eaa6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1336,18 +1336,15 @@ 
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <84000000>;
+				opp-hz = /bits/ 64 <150000000>;
 			};
 			opp01 {
-				opp-hz = /bits/ 64 <167000000>;
+				opp-hz = /bits/ 64 <200000000>;
 			};
 			opp02 {
-				opp-hz = /bits/ 64 <222000000>;
+				opp-hz = /bits/ 64 <300000000>;
 			};
 			opp03 {
-				opp-hz = /bits/ 64 <333000000>;
-			};
-			opp04 {
 				opp-hz = /bits/ 64 <400000000>;
 			};
 		};