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Show patches with
: Submitter =
Dmitry Osipenko
| 791 patches
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Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
[v1,4/5] clk: tegra: emc: Replace BUG() with WARN_ONCE()
clk: tegra: EMC/MC clock fixes and improvements
- - -
-
-
-
2019-04-11
Dmitry Osipenko
Superseded
[v1,3/5] clk: tegra: emc: Fix EMC max-rate clamping
clk: tegra: EMC/MC clock fixes and improvements
- - -
-
-
-
2019-04-11
Dmitry Osipenko
Superseded
[v1,2/5] clk: tegra: emc: Support multiple ram codes parsing
clk: tegra: EMC/MC clock fixes and improvements
- - 1
-
-
-
2019-04-11
Dmitry Osipenko
Superseded
[v1,1/5] clk: tegra: emc: Don't enable EMC clock manually
clk: tegra: EMC/MC clock fixes and improvements
- - -
-
-
-
2019-04-11
Dmitry Osipenko
Awaiting Upstream
[v1,2/2] clk: tegra124: Remove lock-enable bit from PLLM
clk: Tegra124 PLLM fixes
- - 1
-
-
-
2019-04-11
Dmitry Osipenko
Accepted
[v1,1/2] clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
clk: Tegra124 PLLM fixes
- - 1
-
-
-
2019-04-11
Dmitry Osipenko
Accepted
[RE-SEND] clk: tegra: Don't enable already enabled PLLs
[RE-SEND] clk: tegra: Don't enable already enabled PLLs
1 - -
-
-
-
2019-02-24
Dmitry Osipenko
Superseded
[v1] ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30
[v1] ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30
- - -
-
-
-
2019-02-24
Dmitry Osipenko
Not Applicable
[v6,8/8] memory: tegra: Introduce Tegra20 EMC driver
Tegra20 External Memory Controller driver
1 - -
-
-
-
2018-10-21
Dmitry Osipenko
Not Applicable
[v6,7/8] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
Tegra20 External Memory Controller driver
2 - -
-
-
-
2018-10-21
Dmitry Osipenko
Awaiting Upstream
[v6,6/8] clk: tegra20: Turn EMC clock gate into divider
Tegra20 External Memory Controller driver
2 - -
-
-
-
2018-10-21
Dmitry Osipenko
Awaiting Upstream
[v6,5/8] ARM: dts: tegra20: Add clock entry to External Memory Controller
Tegra20 External Memory Controller driver
- - -
-
-
-
2018-10-21
Dmitry Osipenko
Not Applicable
[v6,4/8] ARM: dts: tegra20: Add interrupt entry to External Memory Controller
Tegra20 External Memory Controller driver
1 - -
-
-
-
2018-10-21
Dmitry Osipenko
Not Applicable
[v6,3/8] dt: bindings: Move tegra20-emc binding to memory-controllers directory
Tegra20 External Memory Controller driver
1 - -
-
-
-
2018-10-21
Dmitry Osipenko
Not Applicable
[v6,2/8] dt: bindings: tegra20-emc: Document clock property
Tegra20 External Memory Controller driver
1 - -
-
-
-
2018-10-21
Dmitry Osipenko
Not Applicable
[v6,1/8] dt: bindings: tegra20-emc: Document interrupt property
Tegra20 External Memory Controller driver
2 - -
-
-
-
2018-10-21
Dmitry Osipenko
Not Applicable
[v1,3/3] clk: tegra: Poll PLLX lock-status on resume from suspend on Tegra20/30
CPU clock changes for Tegra20/30
- - -
-
-
-
2018-08-30
Dmitry Osipenko
Changes Requested
[v1,2/3] clk: tegra: Add more rates to Tegra30 PLLX frequency table
CPU clock changes for Tegra20/30
- - -
-
-
-
2018-08-30
Dmitry Osipenko
Rejected
[v1,1/3] clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30
CPU clock changes for Tegra20/30
- - -
-
-
-
2018-08-30
Dmitry Osipenko
Changes Requested
[v2,2/2] clk: tegra20: Enable lock-status polling for PLLs
[v2,1/2] clk: tegra: Don't enable already enabled PLLs
- - -
-
-
-
2018-08-30
Dmitry Osipenko
Changes Requested
[v2,1/2] clk: tegra: Don't enable already enabled PLLs
[v2,1/2] clk: tegra: Don't enable already enabled PLLs
- - -
-
-
-
2018-08-30
Dmitry Osipenko
Changes Requested
[v1,2/2] clk: tegra20: Enable lock-status polling for PLLs
[v1,1/2] clk: tegra: Don't enable already enabled PLLs
- - -
-
-
-
2018-08-18
Dmitry Osipenko
Superseded
[v1,1/2] clk: tegra: Don't enable already enabled PLLs
[v1,1/2] clk: tegra: Don't enable already enabled PLLs
- - -
-
-
-
2018-08-18
Dmitry Osipenko
Superseded
[v5,8/8] memory: tegra: Introduce Tegra20 EMC driver
Tegra20 External Memory Controller driver
1 - -
-
-
-
2018-07-24
Dmitry Osipenko
Not Applicable
[v5,7/8] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
Tegra20 External Memory Controller driver
2 - -
-
-
-
2018-07-24
Dmitry Osipenko
Awaiting Upstream
[v5,6/8] clk: tegra20: Turn EMC clock gate into divider
Tegra20 External Memory Controller driver
2 - -
-
-
-
2018-07-24
Dmitry Osipenko
Awaiting Upstream
[v5,5/8] ARM: dts: tegra20: Add clock entry to External Memory Controller
Tegra20 External Memory Controller driver
- - -
-
-
-
2018-07-24
Dmitry Osipenko
Not Applicable
[v5,4/8] ARM: dts: tegra20: Add interrupt entry to External Memory Controller
Tegra20 External Memory Controller driver
1 - -
-
-
-
2018-07-24
Dmitry Osipenko
Not Applicable
[v5,3/8] dt: bindings: Move tegra20-emc binding to memory-controllers directory
Tegra20 External Memory Controller driver
1 - -
-
-
-
2018-07-24
Dmitry Osipenko
Not Applicable
[v5,2/8] dt: bindings: tegra20-emc: Document clock property
Tegra20 External Memory Controller driver
1 - -
-
-
-
2018-07-24
Dmitry Osipenko
Not Applicable
[v5,1/8] dt: bindings: tegra20-emc: Document interrupt property
Tegra20 External Memory Controller driver
2 - -
-
-
-
2018-07-24
Dmitry Osipenko
Not Applicable
[v4,8/8] memory: tegra: Introduce Tegra20 EMC driver
1 - -
-
-
-
2018-07-19
Dmitry Osipenko
Superseded
[v4,7/8] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
1 - -
-
-
-
2018-07-19
Dmitry Osipenko
Superseded
[v4,6/8] clk: tegra20: Turn EMC clock gate into divider
1 - -
-
-
-
2018-07-19
Dmitry Osipenko
Superseded
[v4,5/8] ARM: dts: tegra20: Add clock entry to External Memory Controller
- - -
-
-
-
2018-07-19
Dmitry Osipenko
Superseded
[v4,4/8] ARM: dts: tegra20: Add interrupt entry to External Memory Controller
1 - -
-
-
-
2018-07-19
Dmitry Osipenko
Superseded
[v4,3/8] dt: bindings: Move tegra20-emc binding to memory-controllers directory
1 - -
-
-
-
2018-07-19
Dmitry Osipenko
Superseded
[v4,2/8] dt: bindings: tegra20-emc: Document clock property
1 - -
-
-
-
2018-07-19
Dmitry Osipenko
Superseded
[v4,1/8] dt: bindings: tegra20-emc: Document interrupt property
2 - -
-
-
-
2018-07-19
Dmitry Osipenko
Superseded
[v3,8/8] memory: tegra: Introduce Tegra20 EMC driver
1 - -
-
-
-
2018-06-17
Dmitry Osipenko
Not Applicable
[v3,7/8] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
1 - -
-
-
-
2018-06-17
Dmitry Osipenko
Superseded
[v3,6/8] clk: tegra20: Turn EMC clock gate into divider
1 - -
-
-
-
2018-06-17
Dmitry Osipenko
Changes Requested
[v3,5/8] ARM: dts: tegra20: Add clock entry to External Memory Controller
- - -
-
-
-
2018-06-17
Dmitry Osipenko
Not Applicable
[v3,4/8] ARM: dts: tegra20: Add interrupt entry to External Memory Controller
1 - -
-
-
-
2018-06-17
Dmitry Osipenko
Not Applicable
[v3,3/8] dt: bindings: Move tegra20-emc binding to memory-controllers directory
1 - -
-
-
-
2018-06-17
Dmitry Osipenko
Not Applicable
[v3,2/8] dt: bindings: tegra20-emc: Document clock property
1 - -
-
-
-
2018-06-17
Dmitry Osipenko
Not Applicable
[v3,1/8] dt: bindings: tegra20-emc: Document interrupt property
2 - -
-
-
-
2018-06-17
Dmitry Osipenko
Not Applicable
[v1] clk: tegra: emc: Avoid out-of-bounds bug
- - -
-
-
-
2018-06-05
Dmitry Osipenko
Accepted
[v1] clk: tegra: Mark Memory Controller clock as critical
1 - -
-
-
-
2018-06-03
Dmitry Osipenko
Accepted
[v2,5/5] memory: tegra: Introduce Tegra20 EMC driver
- - -
-
-
-
2018-06-03
Dmitry Osipenko
Not Applicable
[v2,4/5] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
- - -
-
-
-
2018-06-03
Dmitry Osipenko
Superseded
[v2,3/5] clk: tegra20: Turn EMC clock gate into divider
- - -
-
-
-
2018-06-03
Dmitry Osipenko
Superseded
[v2,2/5] ARM: dts: tegra20: Add interrupt to External Memory Controller
- - -
-
-
-
2018-06-03
Dmitry Osipenko
Not Applicable
[v2,1/5] dt: bindings: tegra20-emc: Document interrupt property
1 - -
-
-
-
2018-06-03
Dmitry Osipenko
Superseded
[v1,4/4] memory: tegra: Introduce Tegra20 EMC driver
- - -
-
-
-
2018-05-30
Dmitry Osipenko
Not Applicable
[v1,3/4] clk: tegra20: Turn EMC clock gate into divider
- - -
-
-
-
2018-05-30
Dmitry Osipenko
Superseded
[v1,2/4] ARM: dts: tegra20: Add interrupt to External Memory Controller
- - -
-
-
-
2018-05-30
Dmitry Osipenko
Not Applicable
[v1,1/4] dt: bindings: tegra20-emc: Document interrupt property
- - -
-
-
-
2018-05-30
Dmitry Osipenko
Not Applicable
[v3,4/4] ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"
- 1 2
-
-
-
2018-05-08
Dmitry Osipenko
Awaiting Upstream
[v3,3/4] clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
1 - -
-
-
-
2018-05-08
Dmitry Osipenko
Awaiting Upstream
[v3,2/4] clk: tegra20: Correct parents of CDEV1/2 clocks
2 1 2
-
-
-
2018-05-08
Dmitry Osipenko
Awaiting Upstream
[v3] pinctrl: tegra20: Provide CDEV1/2 clock muxes
2 1 2
-
-
-
2018-05-08
Dmitry Osipenko
Awaiting Upstream
[v3,1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers
2 1 2
-
-
-
2018-05-08
Dmitry Osipenko
Awaiting Upstream
[v2,4/4] ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"
- 1 2
-
-
-
2018-05-03
Dmitry Osipenko
Superseded
[v2,3/4] clk: tegra: Add quirk for getting CDEV1/2 clocks
- - -
-
-
-
2018-05-03
Dmitry Osipenko
Superseded
[v2,2/4] clk: tegra20: Correct parents of CDEV1/2 clocks
2 1 2
-
-
-
2018-05-03
Dmitry Osipenko
Superseded
[v2] pinctrl: tegra20: Provide CDEV1/2 clock muxes
1 1 2
-
-
-
2018-05-03
Dmitry Osipenko
Not Applicable
[v2,1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers
2 1 2
-
-
-
2018-05-03
Dmitry Osipenko
Superseded
[v1,4/4] ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"
- - -
-
-
-
2018-04-26
Dmitry Osipenko
Not Applicable
[v1,3/4] clk: tegra20: Set correct parents for CDEV1/2 clocks
2 - -
-
-
-
2018-04-26
Dmitry Osipenko
Superseded
[v1,2/4] pinctrl: tegra20: Provide CDEV1/2 clock muxes
1 - -
-
-
-
2018-04-26
Dmitry Osipenko
Not Applicable
[v1,1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers
- 1 1
-
-
-
2018-04-26
Dmitry Osipenko
Superseded
[v3,3/3] clk: tegra: Specify VDE clock rate
1 - -
-
-
-
2018-01-10
Dmitry Osipenko
Awaiting Upstream
[v3,2/3] clk: tegra20: Correct PLL_C_OUT1 setup
1 - -
-
-
-
2018-01-10
Dmitry Osipenko
Awaiting Upstream
[v3,1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical
1 - -
-
-
-
2018-01-10
Dmitry Osipenko
Awaiting Upstream
[v2,2/2] clk: tegra20: Correct PLL_C_OUT1 setup
1 - -
-
-
-
2017-12-19
Dmitry Osipenko
Awaiting Upstream
[v2,1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical
1 - -
-
-
-
2017-12-19
Dmitry Osipenko
Changes Requested
[v1,2/2] clk: tegra20: Correct PLL_C_OUT1 setup
1 - -
-
-
-
2017-12-11
Dmitry Osipenko
Awaiting Upstream
[v1] clk: tegra: Specify VDE clock rate
1 - -
-
-
-
2017-12-11
Dmitry Osipenko
Awaiting Upstream
[v1,1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical
1 - -
-
-
-
2017-12-11
Dmitry Osipenko
Rejected
[v1] clk: tegra20: Add 216 MHz entry for PLL_X
- - -
-
-
-
2017-12-11
Dmitry Osipenko
Rejected
clk: tegra: Mark APB clock as critical
- - -
-
-
-
2017-11-30
Dmitry Osipenko
Rejected
[v2,4/4] clk: tegra20: Bump SCLK clock rate to 216MHz
1 - -
-
-
-
2017-10-03
Dmitry Osipenko
Awaiting Upstream
[v2,3/4] clk: tegra20: Use common definition of APBDMA clock gate
- - -
-
-
-
2017-10-03
Dmitry Osipenko
Awaiting Upstream
[v2,2/4] clk: tegra: Correct parent of the APBDMA clock
- - -
-
-
-
2017-10-03
Dmitry Osipenko
Awaiting Upstream
[v2,1/4] clk: tegra: Add AHB DMA clock entry
- - -
-
-
-
2017-10-03
Dmitry Osipenko
Awaiting Upstream
[v1,5/5] ARM: dts: tegra: Add AHB DMA controller nodes
- - -
-
-
-
2017-09-25
Dmitry Osipenko
Changes Requested
[v1,4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller
- - -
-
-
-
2017-09-25
Dmitry Osipenko
Changes Requested
[v1,3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller
- - -
-
-
-
2017-09-25
Dmitry Osipenko
Changes Requested
[v1,2/5] clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20
1 - -
-
-
-
2017-09-25
Dmitry Osipenko
Changes Requested
[v1,1/5] clk: tegra: Add AHB DMA clock entry
- - -
-
-
-
2017-09-25
Dmitry Osipenko
Changes Requested
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