Message ID | 1595403506-8209-2-git-send-email-claudiu.beznea@microchip.com (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | clk: at91: add sama7g5 clock support | expand |
Quoting Claudiu Beznea (2020-07-22 00:38:09) > __clk_determine_rate() may return error. Skip the current step > in case of error. > > Fixes: 1a1a36d72e3d3 ("clk: at91: clk-generated: make gclk determine audio_pll rate") > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- Applied to clk-next
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 44a46dcc0518..995a13133cfb 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -170,7 +170,8 @@ static int clk_generated_determine_rate(struct clk_hw *hw, for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { req_parent.rate = req->rate * div; - __clk_determine_rate(parent, &req_parent); + if (__clk_determine_rate(parent, &req_parent)) + continue; clk_generated_best_diff(req, parent, req_parent.rate, div, &best_diff, &best_rate);