Message ID | 1595403506-8209-5-git-send-email-claudiu.beznea@microchip.com (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | clk: at91: add sama7g5 clock support | expand |
Quoting Claudiu Beznea (2020-07-22 00:38:12) > Use logical or for range check. In case bestrate is not in > characteristics->output[0].min..characteristics->output[0].max > range we should return -ERANGE. > > Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- Applied to clk-next
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 3522eae2edd6..4b7b6c435d4e 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -231,7 +231,7 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll, } /* Check if bestrate is a valid output rate */ - if (bestrate < characteristics->output[0].min && + if (bestrate < characteristics->output[0].min || bestrate > characteristics->output[0].max) return -ERANGE;