diff mbox series

[011/120] MIPS: R5900: Avoid pipeline hazard with the TLBP instruction

Message ID d3b43e48be1b888c4bd675dc4c0633dc1e8fe791.1567326213.git.noring@nocrew.org (mailing list archive)
State RFC
Headers show
Series Linux for the PlayStation 2 | expand

Commit Message

Fredrik Noring Sept. 1, 2019, 3:40 p.m. UTC
On the R5900, the TLBP instruction must be immediately followed by an
ERET or a SYNC.P instruction[1].

References:

[1] "TX System RISC TX79 Core Architecture" manual, revision 2.0,
    Toshiba Corporation, p. C-37, https://wiki.qemu.org/File:C790.pdf

Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
 arch/mips/mm/tlbex.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Sergei Shtylyov Sept. 1, 2019, 5:15 p.m. UTC | #1
Hello!

On 01.09.2019 18:40, Fredrik Noring wrote:

> On the R5900, the TLBP instruction must be immediately followed by an
> ERET or a SYNC.P instruction[1].
> 
> References:
> 
> [1] "TX System RISC TX79 Core Architecture" manual, revision 2.0,
>      Toshiba Corporation, p. C-37, https://wiki.qemu.org/File:C790.pdf
> 
> Signed-off-by: Fredrik Noring <noring@nocrew.org>
> ---
>   arch/mips/mm/tlbex.c | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
> 
> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
> index 82136c346885..0519e2eafbb8 100644
> --- a/arch/mips/mm/tlbex.c
> +++ b/arch/mips/mm/tlbex.c
> @@ -489,6 +489,19 @@ static void __maybe_unused build_tlb_probe_entry(u32 **p)
>   		uasm_i_tlbp(p);
>   		break;
>   
> +	case CPU_R5900:
> +		/*
> +		 * On the R5900, the TLBWP instruction must be immediately

   So is it TLBP or TLBWP?

> +		 * followed by an ERET or a SYNC.P instruction.
> +		 */
> +		uasm_i_tlbp(p);
> +		uasm_i_syncp(p);
> +		uasm_i_nop(p);
> +		uasm_i_nop(p);
> +		uasm_i_nop(p);
> +		uasm_i_nop(p);
> +		break;
> +
>   	default:
>   		uasm_i_tlbp(p);
>   		break;

MBR, Sergei
Fredrik Noring Sept. 1, 2019, 5:36 p.m. UTC | #2
Hi Sergei,

> > +	case CPU_R5900:
> > +		/*
> > +		 * On the R5900, the TLBWP instruction must be immediately
> 
>    So is it TLBP or TLBWP?

TLBWP does not exist, so it must be TLBP. Thanks! :)

Fredrik
diff mbox series

Patch

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 82136c346885..0519e2eafbb8 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -489,6 +489,19 @@  static void __maybe_unused build_tlb_probe_entry(u32 **p)
 		uasm_i_tlbp(p);
 		break;
 
+	case CPU_R5900:
+		/*
+		 * On the R5900, the TLBWP instruction must be immediately
+		 * followed by an ERET or a SYNC.P instruction.
+		 */
+		uasm_i_tlbp(p);
+		uasm_i_syncp(p);
+		uasm_i_nop(p);
+		uasm_i_nop(p);
+		uasm_i_nop(p);
+		uasm_i_nop(p);
+		break;
+
 	default:
 		uasm_i_tlbp(p);
 		break;