| Message ID | 20231214072839.2367-1-minda.chen@starfivetech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Refactoring Microchip PCIe driver and add StarFive PCIe | expand |
Minda Chen <minda.chen@starfivetech.com> writes: > This patchset final purpose is add PCIe driver for StarFive JH7110 SoC. > JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the > same IP and have commit their codes, which are mixed with PLDA > controller codes and Microchip platform codes. Thank you for this series. I tested this on a VisionFive v2 board, and it seems to probe and find my M.2 NVMe SSD, but then gets timeouts when trying to use the NVMe (e.g. 'blkid' command) Kernel logs below. Kevin [ 15.131094] pcie-starfive 9c0000000.pcie: host bridge /soc/pcie@9c0000000 ranges: [ 15.138637] pcie-starfive 9c0000000.pcie: MEM 0x0038000000..0x003fffffff -> 0x0038000000 [ 15.147180] pcie-starfive 9c0000000.pcie: MEM 0x0980000000..0x09bfffffff -> 0x0980000000 [ 15.368040] pcie-starfive 9c0000000.pcie: port link up [ 15.374219] pcie-starfive 9c0000000.pcie: PCI host bridge to bus 0001:00 [ 15.380944] pci_bus 0001:00: root bus resource [bus 00-ff] [ 15.386443] pci_bus 0001:00: root bus resource [mem 0x38000000-0x3fffffff] [ 15.393330] pci_bus 0001:00: root bus resource [mem 0x980000000-0x9bfffffff pref] [ 15.400882] pci 0001:00:00.0: [1556:1111] type 01 class 0x060400 [ 15.407165] pci 0001:00:00.0: supports D1 D2 [ 15.411447] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 15.419964] pci 0001:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 15.428245] pci 0001:01:00.0: [126f:2263] type 00 class 0x010802 [ 15.434331] pci 0001:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit] [ 15.441578] pci 0001:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x1 link at 0001:00:00.0 (capable of 31.504 Gb/s with 8 .0 GT/s PCIe x4 link) [ 15.456910] pci_bus 0001:01: busn_res: [bus 01-ff] end is updated to 01 [ 15.463553] pci 0001:00:00.0: BAR 8: assigned [mem 0x38000000-0x380fffff] [ 15.470352] pci 0001:01:00.0: BAR 0: assigned [mem 0x38000000-0x38003fff 64bit] [ 15.477699] pci 0001:00:00.0: PCI bridge to [bus 01] [ 15.482686] pci 0001:00:00.0: bridge window [mem 0x38000000-0x380fffff] [ 15.489632] pcieport 0001:00:00.0: enabling device (0000 -> 0002) [ 15.496038] pcieport 0001:00:00.0: PME: Signaling with IRQ 56 [ 15.502472] usb 1-1: new high-speed USB device number 2 using xhci_hcd [ 15.509755] usb usb2-port2: over-current condition [ 15.515883] nvme nvme0: pci function 0001:01:00.0 [ 15.520615] nvme 0001:01:00.0: enabling device (0000 -> 0002) [ 15.532685] nvme nvme0: allocated 64 MiB host memory buffer. [ 15.550070] nvme nvme0: 4/0/0 default/read/poll queues [ 15.562992] nvme nvme0: Ignoring bogus Namespace Identifiers [ 15.663327] hub 1-1:1.0: USB hub found [ 15.667320] hub 1-1:1.0: 4 ports detected [ 46.064052] nvme nvme0: I/O 424 QID 3 timeout, completion polled [ 76.784046] nvme nvme0: I/O 425 (I/O Cmd) QID 3 timeout, aborting [ 76.790179] nvme nvme0: I/O 426 (I/O Cmd) QID 3 timeout, aborting [ 76.796294] nvme nvme0: I/O 427 (I/O Cmd) QID 3 timeout, aborting [ 76.802411] nvme nvme0: I/O 428 (I/O Cmd) QID 3 timeout, aborting [ 76.808525] nvme nvme0: I/O 429 (I/O Cmd) QID 3 timeout, aborting
> Minda Chen <minda.chen@starfivetech.com> writes: > > > This patchset final purpose is add PCIe driver for StarFive JH7110 SoC. > > JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the > > same IP and have commit their codes, which are mixed with PLDA > > controller codes and Microchip platform codes. > > Thank you for this series. > > I tested this on a VisionFive v2 board, and it seems to probe and find my > M.2 NVMe SSD, but then gets timeouts when trying to use the NVMe (e.g. > 'blkid' command) > Hi, Kevin: Could you please provide the manufacturer and model of the M.2 NVMe SSD you tested? > Kernel logs below. > > Kevin > > [ 15.131094] pcie-starfive 9c0000000.pcie: host bridge > /soc/pcie@9c0000000 ranges: > [ 15.138637] pcie-starfive 9c0000000.pcie: MEM > 0x0038000000..0x003fffffff -> 0x0038000000 > [ 15.147180] pcie-starfive 9c0000000.pcie: MEM > 0x0980000000..0x09bfffffff -> 0x0980000000 > [ 15.368040] pcie-starfive 9c0000000.pcie: port link up > [ 15.374219] pcie-starfive 9c0000000.pcie: PCI host bridge to bus 0001:00 > [ 15.380944] pci_bus 0001:00: root bus resource [bus 00-ff] > [ 15.386443] pci_bus 0001:00: root bus resource [mem > 0x38000000-0x3fffffff] > [ 15.393330] pci_bus 0001:00: root bus resource [mem > 0x980000000-0x9bfffffff pref] > [ 15.400882] pci 0001:00:00.0: [1556:1111] type 01 class 0x060400 > [ 15.407165] pci 0001:00:00.0: supports D1 D2 > [ 15.411447] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot > D3cold > [ 15.419964] pci 0001:00:00.0: bridge configuration invalid ([bus 00-00]), > reconfiguring > [ 15.428245] pci 0001:01:00.0: [126f:2263] type 00 class 0x010802 > [ 15.434331] pci 0001:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff > 64bit] > [ 15.441578] pci 0001:01:00.0: 4.000 Gb/s available PCIe bandwidth, > limited by 5.0 GT/s PCIe x1 link at 0001:00:00.0 (capable of 31.504 Gb/s with > 8 > .0 GT/s PCIe x4 link) > [ 15.456910] pci_bus 0001:01: busn_res: [bus 01-ff] end is updated to 01 > [ 15.463553] pci 0001:00:00.0: BAR 8: assigned [mem > 0x38000000-0x380fffff] > [ 15.470352] pci 0001:01:00.0: BAR 0: assigned [mem > 0x38000000-0x38003fff 64bit] > [ 15.477699] pci 0001:00:00.0: PCI bridge to [bus 01] > [ 15.482686] pci 0001:00:00.0: bridge window [mem > 0x38000000-0x380fffff] > [ 15.489632] pcieport 0001:00:00.0: enabling device (0000 -> 0002) > [ 15.496038] pcieport 0001:00:00.0: PME: Signaling with IRQ 56 > [ 15.502472] usb 1-1: new high-speed USB device number 2 using xhci_hcd > [ 15.509755] usb usb2-port2: over-current condition > [ 15.515883] nvme nvme0: pci function 0001:01:00.0 > [ 15.520615] nvme 0001:01:00.0: enabling device (0000 -> 0002) > [ 15.532685] nvme nvme0: allocated 64 MiB host memory buffer. > [ 15.550070] nvme nvme0: 4/0/0 default/read/poll queues > [ 15.562992] nvme nvme0: Ignoring bogus Namespace Identifiers > [ 15.663327] hub 1-1:1.0: USB hub found > [ 15.667320] hub 1-1:1.0: 4 ports detected > > [ 46.064052] nvme nvme0: I/O 424 QID 3 timeout, completion polled > > [ 76.784046] nvme nvme0: I/O 425 (I/O Cmd) QID 3 timeout, aborting > [ 76.790179] nvme nvme0: I/O 426 (I/O Cmd) QID 3 timeout, aborting > [ 76.796294] nvme nvme0: I/O 427 (I/O Cmd) QID 3 timeout, aborting > [ 76.802411] nvme nvme0: I/O 428 (I/O Cmd) QID 3 timeout, aborting > [ 76.808525] nvme nvme0: I/O 429 (I/O Cmd) QID 3 timeout, aborting
Kevin Xie <kevin.xie@starfivetech.com> writes: >> Minda Chen <minda.chen@starfivetech.com> writes: >> >> > This patchset final purpose is add PCIe driver for StarFive JH7110 SoC. >> > JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the >> > same IP and have commit their codes, which are mixed with PLDA >> > controller codes and Microchip platform codes. >> >> Thank you for this series. >> >> I tested this on a VisionFive v2 board, and it seems to probe and find my >> M.2 NVMe SSD, but then gets timeouts when trying to use the NVMe (e.g. >> 'blkid' command) >> > > Hi, Kevin: > Could you please provide the manufacturer and model of the M.2 NVMe SSD > you tested? I have a 256 Gb Silicon Power P34A60 M.2 NVMe SSD (part number: sp256gbp34a60m28) Also for reference, I tested the same SSD on another arm platform (Khadas VIM3) and it works fine. Kevin
This patchset final purpose is add PCIe driver for StarFive JH7110 SoC. JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the same IP and have commit their codes, which are mixed with PLDA controller codes and Microchip platform codes. For re-use the PLDA controller codes, I request refactoring microchip codes, move PLDA common codes to PLDA files. Desigware and Cadence is good example for refactoring codes. ---------------------------------------------------------- The refactoring patches total number is 16,(patch 1-16) which do NOT contain changing logic of codes. These patches just contain three type basic operations. (rename, modify codes to support starfive platform, and moving to common file) If these patched are all be reviewed. They can be accepted first. Refactoring patches can be devided to different groups 1. (patch 1- 3 is the prepare work of refactoring) patch1 is move PLDA XpressRICH PCIe host common properties dt-binding docs from microchip,pcie-host.yaml patch2 is move PolarFire codes to PLDA directory. patch3 is move PLDA IP register macros to plda-pcie.h 2. (patch4 - 6 is processing and re-use PCIe host instance) patch4 is add bridge_addr field to PCIe host instance. patch5 is rename data structure in microchip codes. patch6 is moving two data structures to head file 3. (patch 7 - 9 are for re-use two PCIe setup function) patch7 is rename two setup functions in microchip codes, prepare to move to common file. patch8 is change the arguments of plda_pcie_setup_iomems() patch9 is move the two setup functions to common file pcie-plda-host.c 4.(patch 10 - 16 are for re-use interupt processing codes) patch10 is rename the IRQ related functions, prepare to move to pcie-plda-host.c patch 11 - 15 is modify the interrupt event codes, preparing for support starfive and microchip two platforms. patch16 is move IRQ related functions to pcie-plda-host.c ------------------------------------------------------------ The remainder patches (patch 17 -21) are not refactoring patch. They are for adding StarFive codes and dont modify the microchip's codes. patch17 is Add host init/deinit functions. patch18 is add StarFive JH7110 PCIe dt-binding doc. patch19 is Add a PCIe delay time macro patch20 is add StarFive JH7110 Soc PCIe codes. patch21 is Starfive dts config This patchset is base on v6.7-rc4 previous version: v6:https://patchwork.kernel.org/project/linux-pci/cover/20230915102243.59775-1-minda.chen@starfivetech.com/ v7:https://patchwork.kernel.org/project/linux-pci/cover/20230927100802.46620-1-minda.chen@starfivetech.com/ v8:https://patchwork.kernel.org/project/linux-pci/cover/20231011110514.107528-1-minda.chen@starfivetech.com/ v9:https://patchwork.kernel.org/project/linux-pci/cover/20231020104341.63157-1-minda.chen@starfivetech.com/ v10:https://patchwork.kernel.org/project/linux-pci/cover/20231031115430.113586-1-minda.chen@starfivetech.com/ v11:https://patchwork.kernel.org/project/linux-pci/cover/20231115114912.71448-1-minda.chen@starfivetech.com/ v12:https://patchwork.kernel.org/project/linux-pci/cover/20231206105839.25805-1-minda.chen@starfivetech.com/ change: v13: patch14: 1. Add plda_get_event() function. This can be compare with mc_get_event() easily and track the codes changes in case in the future.. 2. The host event_ops is directly set to plda host port. 3. Setting default host event_ops instead of checking event ops. patch15:1. Add PLDA event irq_chip instead of event_domain_ops, The event_domain_ops can be re-used. 2. The host event irq_chip is directly set to plda host port. 3. Add PLDA event irqchip ops codes. 4. Remove Conor's review tag due to whole patch have been changed. patch16: Also move the new added PLDA event codes. patch17: Add plda host init and deinit function only. v12: patch17: modify the commit message and add starfive review tag. Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS to patch 19. patch20: Add disable runtime pm function in starfive_pcie_remove() Add "depens on ARCH_STARFIVE || COMPILE_TEST" in Starfive PCie Kconfig v11: check and modify some commit messages again. All the codes are the same with v10. v10: All the commit message set to fit in 75 columns. All the codes fit in less than 80 colunms. patch 14: Commit message changes suggested by Conor. patch 20: Add 100 ms delay macro to pci.h generic phy pointer related codes moving to pcie-starfive.c This patch Change pcie-starfive only, bus_ops move to patch 16. Some Codes changes suggested by Bjorn. v9: v8 patch 10 squash to v9 patch 12, v8 patch 18 squash to v9 patch 16. patch 4 - 16: Add new review tags and add more accurate commit messages. patch 17: move the plda_pcie_host_init/deinit from patch 19. Make plda driver become to whole driver. v8: The patch description in cover-letter has been changed. v7 patch 4 split to v8 patch 4 - 6. (It is patches about re-use pcie host data structure, new patches just contain one function modification. It is more reguluar and easier to review). patch 7- 9: modify the commit messages and add reason of modifcation. patch10- 16 : Add review tag and add more commit messages to declear the reason of modifying the codes. patch17: plda_handle_events() using bit mask macro. The function are easier to read. v7: patch17: fix the build warning. patch20: Some format changes (Emil's comment) patch21: change the pcie node sequences by alphabetical delete the "interupt-parent" in pcie node. v6: v5 patch 4 split to patch 4 -9. New patches just contain one function modification. It is more reguluar. patch 9: Just move the two setup functions only patch 19 : draw a graph of PLDA local register, make it easier to review the codes. v5 patch 7 split to patch 10- 16. Each patch just contain one function modification. It is more regular. patch 10: rename IRQ related functions. patch 11 - 15 : modify the events codes, total five patch. patch 16: move IRQ related functions to pcie-plda-host.c patch 20- 21 using "linux,pci-domain" dts setting. Kevin Xie (1): PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Minda Chen (20): dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties PCI: microchip: Move pcie-microchip-host.c to plda directory PCI: microchip: Move PLDA IP register macros to pcie-plda.h PCI: microchip: Add bridge_addr field to struct mc_pcie PCI: microchip: Rename two PCIe data structures PCI: microchip: Move PCIe host data structures to plda-pcie.h PCI: microchip: Rename two setup functions PCI: microchip: Change the argument of plda_pcie_setup_iomems() PCI: microchip: Move setup functions to pcie-plda-host.c PCI: microchip: Rename interrupt related functions PCI: microchip: Add num_events field to struct plda_pcie_rp PCI: microchip: Add request_event_irq() callback function PCI: microchip: Add INTx and MSI event num to struct plda_event PCI: microchip: Add get_events() callback and add PLDA get_event() PCI: microchip: Add event irqchip field to host port and add PLDA irqchip PCI: microchip: Move IRQ functions to pcie-plda-host.c PCI: plda: Add host init/deinit and map bus functions dt-bindings: PCI: Add StarFive JH7110 PCIe controller PCI: starfive: Add JH7110 PCIe controller riscv: dts: starfive: add PCIe dts configuration for JH7110 .../bindings/pci/microchip,pcie-host.yaml | 55 +- .../pci/plda,xpressrich3-axi-common.yaml | 75 ++ .../bindings/pci/starfive,jh7110-pcie.yaml | 120 ++++ MAINTAINERS | 19 +- .../jh7110-starfive-visionfive-2.dtsi | 64 ++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++ drivers/pci/controller/Kconfig | 9 +- drivers/pci/controller/Makefile | 2 +- drivers/pci/controller/plda/Kconfig | 30 + drivers/pci/controller/plda/Makefile | 4 + .../{ => plda}/pcie-microchip-host.c | 614 ++-------------- drivers/pci/controller/plda/pcie-plda-host.c | 656 ++++++++++++++++++ drivers/pci/controller/plda/pcie-plda.h | 265 +++++++ drivers/pci/controller/plda/pcie-starfive.c | 462 ++++++++++++ drivers/pci/pci.h | 16 + 15 files changed, 1861 insertions(+), 616 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml create mode 100644 drivers/pci/controller/plda/Kconfig create mode 100644 drivers/pci/controller/plda/Makefile rename drivers/pci/controller/{ => plda}/pcie-microchip-host.c (54%) create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c create mode 100644 drivers/pci/controller/plda/pcie-plda.h create mode 100644 drivers/pci/controller/plda/pcie-starfive.c base-commit: 33cc938e65a98f1d29d0a18403dbbee050dcad9a