| Message ID | 20231208105155.36097-1-krzysztof.kozlowski@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | [v3,1/4] dt-bindings: PCI: qcom: adjust iommu-map for different SoC | expand |
Hello,
Applied to dt-bindings, thank you!
[01/04] dt-bindings: PCI: qcom: Adjust iommu-map for different SoC
https://git.kernel.org/pci/pci/c/4791c44c0a98
[02/04] dt-bindings: PCI: qcom: Correct clocks for SC8180x
https://git.kernel.org/pci/pci/c/f2ab5a2455d9
[03/04] dt-bindings: PCI: qcom: Correct clocks for SM8150
https://git.kernel.org/pci/pci/c/a711253d5f70
The above will go through the PCI tree.
Krzysztof
On Fri, 08 Dec 2023 11:51:52 +0100, Krzysztof Kozlowski wrote: > The PCIe controller on SDX55 has five entries in its iommu-map, MSM8998 > has one and SDM845 has sixteen, so allow wider number of items to fix > dtbs_check warnings like: > > qcom-sdx55-mtp.dtb: pcie@1c00000: iommu-map: [[0, 21, 512, 1], [256, 21, 513, 1], > [512, 21, 514, 1], [768, 21, 515, 1], [1024, 21, 516, 1]] is too long > > [...] Applied, thanks! [4/4] arm64: dts: qcom: sm8150: add necessary ref clock to PCIe commit: 6de995bc46344d5a6f0c80fee526bfb5d11c3d88 Best regards,
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 9dbc07dfd48f..5056da499f04 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -66,7 +66,8 @@ properties: maxItems: 8 iommu-map: - maxItems: 2 + minItems: 1 + maxItems: 16 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later.
The PCIe controller on SDX55 has five entries in its iommu-map, MSM8998 has one and SDM845 has sixteen, so allow wider number of items to fix dtbs_check warnings like: qcom-sdx55-mtp.dtb: pcie@1c00000: iommu-map: [[0, 21, 512, 1], [256, 21, 513, 1], [512, 21, 514, 1], [768, 21, 515, 1], [1024, 21, 516, 1]] is too long Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Please take the patch via PCI tree. Changes in v3: 1. None Changes in v2: 1. Add Acs/Rb. --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)