mbox series

[v2,0/3] Allow accessing CSR using CSR number

Message ID 20190413153807.116227-1-anup.patel@wdc.com (mailing list archive)
Headers show
Series Allow accessing CSR using CSR number | expand

Message

Anup Patel April 13, 2019, 3:38 p.m. UTC
This patch series adds support to access CSR using both CSR name and
CSR numbers.

Also, we should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
   as-per RISC-V spec. (e.g. sptbr => CSR_SATP, sbadaddr => CSR_STVAL, etc.)
3. We can access newly added CSRs even if toolchain does not recognize
   newly addes CSRs by name. (e.g. BSSTATUS, BSIE, SSIP, etc.)

The patchset can be found in riscv_csr_number_v2 branch of
https//github.com/avpatel/linux.git

Changes since v1:
 - Squash PATCH2 into cpatch3
 - Added new PATCH2 to add interrupt related SCAUSE defines
   in asm/encoding.h

Anup Patel (3):
  RISC-V: Add separate asm/encoding.h for spec related defines
  RISC-V: Add interrupt related SCAUSE defines in asm/encoding.h
  RISC-V: Access CSRs using CSR numbers

 arch/riscv/include/asm/csr.h         | 67 +++-----------------
 arch/riscv/include/asm/encoding.h    | 95 ++++++++++++++++++++++++++++
 arch/riscv/include/asm/irqflags.h    | 10 +--
 arch/riscv/include/asm/mmu_context.h |  7 +-
 arch/riscv/kernel/entry.S            | 22 +++----
 arch/riscv/kernel/head.S             | 12 ++--
 arch/riscv/kernel/irq.c              |  9 +--
 arch/riscv/kernel/perf_event.c       |  4 +-
 arch/riscv/kernel/smp.c              |  2 +-
 arch/riscv/kernel/traps.c            |  6 +-
 arch/riscv/mm/fault.c                |  6 +-
 11 files changed, 139 insertions(+), 101 deletions(-)
 create mode 100644 arch/riscv/include/asm/encoding.h

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2.17.1