[v2,0/9] Add Sipeed Lichee Pi 4A RISC-V board support

Message

Jisheng Zhang May 18, 2023, 6:45 p.m. UTC

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's TH1520 SoC. Add minimal device
tree files for the core module and the development board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.

FWICT, one issue I'm not sure is the cpu reset dt-binding: IIUC, the
secondary CPUs in T-HEAD SMP capable platforms need some special
handling. The first one is to write the warm reset entry to entry
register. The second one is write a SoC specific control value to
a SoC specific control reg. The last one is to clone some CSRs for
secondary CPUs to ensure these CSRs' values are the same as the
main boot CPU. This DT node is mainly used by opensbi firmware.
Any suggestion about this reset dt-binding is appreciated!

Thanks

Since v1:
  - add missing plic, clint, th1520 itself dt-bindings
  - use c900-plic
  - s/light/th1520
  - add dt-binding for T-HEAD CPU reset
  - enable ARCH_THEAD in defconfig
  - fix all dtbs_check error/warning except the CPU RESET, see above.

Jisheng Zhang (9):
  dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
  dt-bindings: timer: Add T-HEAD TH1520 clint
  dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
  dt-binding: riscv: add T-HEAD CPU reset
  riscv: Add the T-HEAD SoC family Kconfig option
  riscv: dts: add initial T-HEAD TH1520 SoC device tree
  riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
  MAINTAINERS: add entry for T-HEAD RISC-V SoC
  riscv: defconfig: enable T-HEAD SoC

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../bindings/riscv/thead,cpu-reset.yaml       |  69 +++
 .../devicetree/bindings/riscv/thead.yaml      |  29 ++
 .../bindings/timer/sifive,clint.yaml          |   1 +
 MAINTAINERS                                   |   6 +
 arch/riscv/Kconfig.socs                       |   6 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/thead/Makefile            |   2 +
 .../dts/thead/th1520-lichee-module-4a.dtsi    |  38 ++
 .../boot/dts/thead/th1520-lichee-pi-4a.dts    |  32 ++
 arch/riscv/boot/dts/thead/th1520.dtsi         | 451 ++++++++++++++++++
 arch/riscv/configs/defconfig                  |   1 +
 12 files changed, 637 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
 create mode 100644 arch/riscv/boot/dts/thead/Makefile
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
 create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
 create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi

Comments

Yixun Lan May 26, 2023, 2:19 a.m. UTC | #1

Hi Jisheng
On 02:45 Fri 19 May     , Jisheng Zhang wrote:
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's TH1520 SoC. Add minimal device
> tree files for the core module and the development board.
> 
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.
> 
> FWICT, one issue I'm not sure is the cpu reset dt-binding: IIUC, the
> secondary CPUs in T-HEAD SMP capable platforms need some special
> handling. The first one is to write the warm reset entry to entry
> register. The second one is write a SoC specific control value to
> a SoC specific control reg. The last one is to clone some CSRs for
> secondary CPUs to ensure these CSRs' values are the same as the
> main boot CPU. This DT node is mainly used by opensbi firmware.
> Any suggestion about this reset dt-binding is appreciated!
> 
> Thanks
> 
> Since v1:
>   - add missing plic, clint, th1520 itself dt-bindings
>   - use c900-plic
>   - s/light/th1520
>   - add dt-binding for T-HEAD CPU reset
>   - enable ARCH_THEAD in defconfig
>   - fix all dtbs_check error/warning except the CPU RESET, see above.
it would be nice to have a URL reference to v0
https://lore.kernel.org/all/[e-mail]/

> 
> Jisheng Zhang (9):
>   dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
>   dt-bindings: timer: Add T-HEAD TH1520 clint
>   dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
>   dt-binding: riscv: add T-HEAD CPU reset
>   riscv: Add the T-HEAD SoC family Kconfig option
>   riscv: dts: add initial T-HEAD TH1520 SoC device tree
>   riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
>   MAINTAINERS: add entry for T-HEAD RISC-V SoC
>   riscv: defconfig: enable T-HEAD SoC
> 
>  .../sifive,plic-1.0.0.yaml                    |   1 +
>  .../bindings/riscv/thead,cpu-reset.yaml       |  69 +++
>  .../devicetree/bindings/riscv/thead.yaml      |  29 ++
>  .../bindings/timer/sifive,clint.yaml          |   1 +
>  MAINTAINERS                                   |   6 +
>  arch/riscv/Kconfig.socs                       |   6 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/thead/Makefile            |   2 +
>  .../dts/thead/th1520-lichee-module-4a.dtsi    |  38 ++
>  .../boot/dts/thead/th1520-lichee-pi-4a.dts    |  32 ++
>  arch/riscv/boot/dts/thead/th1520.dtsi         | 451 ++++++++++++++++++
>  arch/riscv/configs/defconfig                  |   1 +
>  12 files changed, 637 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
>  create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
>  create mode 100644 arch/riscv/boot/dts/thead/Makefile
>  create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
>  create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
>  create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
> 
> -- 
> 2.40.0
> 
> 
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