| Message ID | 20230922062834.39212-1-william.qiu@starfivetech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Change tuning implementation | expand |
On Fri, 22 Sept 2023 at 08:28, William Qiu <william.qiu@starfivetech.com> wrote: > > Hi, > > This series of patches changes the tuning implementation, from the > previous way of reading and writing system controller registers to > reading and writing UHS_REG_EXT register, thus optimizing the tuning > of obtaining delay-chain. > > Changes v2->v3: > - Rebased to v6.6rc2. > - Dropped redundant criteria. > - Keeped "starfive,sysreg" in dts file. > > Changes v1->v2: > - Rebased to v6.6rc1. > - Keeped "starfive,sysreg" in dt-bindings but removed from required. > - Changed the function interface name. > - Maked the code implementation more concise. > > The patch series is based on v6.6rc2. > > William Qiu (3): > dt-bindings: mmc: Remove properties from required > mmc: starfive: Change tuning implementation > riscv: dts: starfive: add assigned-clock* to limit frquency > > .../bindings/mmc/starfive,jh7110-mmc.yaml | 2 - > .../jh7110-starfive-visionfive-2.dtsi | 4 + > drivers/mmc/host/dw_mmc-starfive.c | 137 +++++------------- > 3 files changed, 44 insertions(+), 99 deletions(-) > Patch 1 -> 2 applied for next, thanks! Kind regards Uffe
From: Conor Dooley <conor.dooley@microchip.com> On Fri, 22 Sep 2023 14:28:31 +0800, William Qiu wrote: > This series of patches changes the tuning implementation, from the > previous way of reading and writing system controller registers to > reading and writing UHS_REG_EXT register, thus optimizing the tuning > of obtaining delay-chain. > > Changes v2->v3: > - Rebased to v6.6rc2. > - Dropped redundant criteria. > - Keeped "starfive,sysreg" in dts file. > > [...] Applied to riscv-dt-for-next, thanks! [3/3] riscv: dts: starfive: add assigned-clock* to limit frquency https://git.kernel.org/conor/c/af571133f7ae Thanks, Conor.