| Message ID | 20230922062834.39212-4-william.qiu@starfivetech.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Change tuning implementation | expand |
William Qiu wrote: > In JH7110 SoC, we need to go by-pass mode, so we need add the > assigned-clock* properties to limit clock frquency. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> Thanks! Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > --- > .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index d79f94432b27..d1f2ec308bca 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -205,6 +205,8 @@ &i2c6 { > > &mmc0 { > max-frequency = <100000000>; > + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; > + assigned-clock-rates = <50000000>; > bus-width = <8>; > cap-mmc-highspeed; > mmc-ddr-1_8v; > @@ -221,6 +223,8 @@ &mmc0 { > > &mmc1 { > max-frequency = <100000000>; > + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; > + assigned-clock-rates = <50000000>; > bus-width = <4>; > no-sdio; > no-mmc; > -- > 2.34.1 >
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index d79f94432b27..d1f2ec308bca 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -205,6 +205,8 @@ &i2c6 { &mmc0 { max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + assigned-clock-rates = <50000000>; bus-width = <8>; cap-mmc-highspeed; mmc-ddr-1_8v; @@ -221,6 +223,8 @@ &mmc0 { &mmc1 { max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + assigned-clock-rates = <50000000>; bus-width = <4>; no-sdio; no-mmc;
In JH7110 SoC, we need to go by-pass mode, so we need add the assigned-clock* properties to limit clock frquency. Signed-off-by: William Qiu <william.qiu@starfivetech.com> --- .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++ 1 file changed, 4 insertions(+)